IBM PowerPC 405GP

"Instruction Machine Check Handling" on page 10-35 describes instruction machine checks. "Data
Storage Interrupt" on page 10-36 describes data storage interrupts. "Program Interrupt" on
page
10-40 describes program interrupts.
Although interrupt
handling routines are not required to reset the ESR, it is recommended that
instruction machine check handlers reset the
ESR; "Instruction Machine Check Handling" on
page
10-35 describes why such resets are recommended.
The contents of the
ESR can be written to a GPR using the mfspr instruction. The contents of a GPR
can be written to the
ESR using the mtspr instruction.
Figure
10-15 shows the ESR bit definitions.
Mel
PIL PTR . OIZ
1
0
11
..
3141516f71811·10
* * i
t t
3
1
1
PPR OST
Figure 10-15. Exception Syndrome Register (ESR)
0
MCI
Machine check-instruction
o Instruction machine check did not occur.
1 Instruction machine check occurred .
1:3
..
Reserved
.. ':.:
4
PIL
Program interrupt-illegal
o Illegal Instruction error did not occur.
1 Illegal Instruction error occurred.
5
PPR Program interrupt-privileged
o Privileged instruction error did not occur.
1 Privileged instruction error occurred.
6
PTR
Program
interrupt-trap
o Trap with successful compare did not
occur.
1 Trap with
successful compare occurred .
7
......................... : .........
Reserved
8
DST Data storage interrupt-store fault
o Excepting instruction was not a store.
1 Excepting instruction was a store
(includes dcbi, dcbz, and dccci).
9
DIZ
Data/instruction storage interrupt-zone
fault
o Excepting condition was not a zone fault.
1 Excepting condition was a zone fault.
10:15
I···.·;.·····.········ •• :·····.·.·· ..
Reserved
10-32
PPC405GP User's Manual
Preliminary