Chapter
3.
Programming Model
The programming model of the PPC405GP embedded processor describes the following features
and operations:
• Memory organization and addressing, starting on page
3-1
• Registers, starting on page 3-3
• Data types and alignment, starting on page 3-26
• Byte ordering, starting on page 3-28
• Instruction processing, starting
on
page 3-33
• Branching control, starting
on
page 3-34
• Speculative accesses, starting on page 3-37
• Privileged mode operation, starting on page
3-41
• Synchronization, starting
on
page 3-43
• Instruction set, starting on page 3-47
3.1
User and Privileged Programming Models
The PPC405GP executes programs
in
two modes, also referred to as states. Programs running
in
privileged
mode
(also referred to as the supervisor state) can access any register and execute any
instruction. These instructions and registers comprise the
privileged programming model.
In
user
mode, certain registers and instructions are unavailable to programs. This is also called the problem
state. Those registers and instructions that are available comprise the user programming model.
Privileged
mode provides operating system software access to all processor resources. Because
access to certain processor resources is denied in user mode,
application software runs
in
user
mode. Operating system software and other
application software is protected from the effects of an
errant
application program.
Throughout this book, the terms user program and privileged programs are used to associate
programs with one of the programming
models. Registers and instructions are described as user or
privileged.
Privileged mode operation is described
in
detail
in
"Privileged Mode Operation" on
pag"e
3-41.
3.2 Memory Organization and Addressing
The PowerPC Architecture defines a 32-bit, 4-gigabyte (GB) address space for instructions and data.
Preliminary
Programming Model
3-1
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