6.8 Real-mode Storage Attribute Control
The PowerPC Architecture
"and
the PowerPC Embedded Environment define several SPRs to control
the following storage attributes
in
real mode:
W,
I,
G,UO,
and E. Note that the
UO
and E attributes are
not defined
in
the PowerPC Architecture. The E attribute is defined
in
the IBM PowerPC Embedded
Environment, and the
UO
attribute is implementation-specific. No storage attribute control register is
implemented for the M storage attribute because the
PPC405GP does not provide multi-processor
support or hardware support for data coherency.
These
SPRs, called storage attribute control registers, control the various storage attributes when
address translation is disabled. When address translation is enabled, these registers are ignored, and
the storage attributes supplied by the TLB entry are used (see
"TLB Fields" on page 6-3).
The storage attribute control registers divide the 4GB real address space into thirty-two 128MB
regions.
In
a storage attribute control register, bit 0 controls the lowest addressed 128MB region, bit 1
the next higher-addressed 128MB region, and so on.
EAo:4
specify a storage control region.
For detailed information on the function of the storage attributes, see
"Storage Attribute Fields" on
page 6-5.
Preliminary
Memory Management
6-17
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