3.5.3.1 Fetching Instructions from Little Endian Storage Regions
Instructions are words (four bytes) that are aligned on word boundaries
in
memory. As such,
instructions
in
a big endian memory region are arranged with the most significant byte (MSB) of the
instruction word at the
lowest address.
Consider the big end ian mapping of instruction
p at address
~O,
where, for example,
p = add
r7,
r7,
r4:
On the other hand,
in
the little end ian mapping instruction p is arranged with the least significant byte
.
(LSB) of the instruction word at the lowest numbered address:
When an instruction is fetched from memory, the instruction must be
placed
in
the instruction queue
in
the proper order. The execution unit assumes that the MSB of an instruction word is at the lowest
address. Therefore, when instructions are fetched from little endian storage regions, the four bytes of
an instruction word are reversed before the instruction is decoded.
In
the PPC405GP, the byte
reversal occurs between memory and the instruction cache unit (ICU). The ICU always stores
instructions
in
big end ian format, regardless of whether the memory region containing the instruction
is programmed as big endian or
little endian. Thus, the bytes are already in the proper order when an
instruction is transferred from the
ICU to the decode stage of the pipeline.
If
a storage region is reprogrammed from one end ian format to the other, the storage region must be
reloaded with program and data structures
in
the appropriate endian format. If the endian format of
instruction memory changes, the
ICU must be made coherent with the updates. The ICU must be
invalidated and the updated instruction memory using the new endian format must be fetched so that
the proper byte ordering occurs before the new instructions are
placed in the ICU.
3.5.3.2 Accessing Data in Little Endian Storage Regions
Unlike instruction fetches from little end ian storage regions, data accesses from little end ian storage
regions are
not
byte-reversed between memory and the DCU. Data byte ordering,
in
memory,
depends on the data type (byte,
halfword, or word) of a specific data item.
It
is only when moving a
data item
of
a specific type from or to a GPR that it becomes known what type of byte reversal is
required. Therefore, byte
reversal during load/store accesses is performed between the DCU and the
GPR.
When accessing data
in
a little endian storage region:
• For byte loads/stores, no reordering occurs.
• For halfword loads/stores, bytes are reversed within the halfword.
•
For word loads/stores, bytes are reversed within the word.
Note that this
applies, regardless of data alignment.
Preliminary
Programming Model
3-31
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