IBM PowerPC 405GP

17.5.2.8 PMM 1 PCI High Address Register (PCILO_PMM1 PCIHA)
PCILO_PMM1 PCIHA defines the high-order 32 bits of the PCI address generated in response to a
PLB access to range
1. See "PMM 0 PCI High Address Register (PCILO_PMMOPCIHA)" on
page 17-23.
1
31
Figure 17-14. PMM 0 High Address Register (PCILO_PMMOPCIHA)
I 31:0 I PCI High Address
17.5.2.9 PMM 2 Local Address Register (PCILO_PMM2LA)
PCILO_PMM2LA defines the PLB starting address of range 2 in PLB space that is mapped to PCI
memory. See "PMM 0 Local Address Register (PCILO_PMMOLA)" on page 17-21.
131
Figure 17-15. PMM 2 Local Address Register (PCILO_PMM2LA)
I 31:0 I PLB Local Address
17.5.2.10 PMM 2 Mask/Attribute Register (PCILO_PMM2MA)
PCILO_PMM2MA defines the size and attributes of range 2 in PLB space that is mapped to PCI
memory. See "PMM 0 Mask/Attribute Register (PCILO_PMMOMA)" on page 17-22.
01
01
Preliminary PCI Interface
17-25