IBM PowerPC 405GP

MASK
ENA
1
31
=*
=*
211 0 1
t
PRE
Figure 17-16. PMM 2 Mask/Attribute Register (PCILO_PMM2MA)
31:12 MASK
The mask bits determine the size of the
The mask must be of the form
111 .... 0000.
address map range. Bits set to 1 cause the corresponding
PCILO_PMM2LA bits to be compared with
incoming
PLB addresses. Note that the
minimum range size is 4KB, and
valid
ranges are powers of 2. For example, a
128MB range
would be encoded as
OxF8000 and a 4KB range would be
encoded as Ox11111.
11 :2
,
Reserved
Returns 0 when read.
...
1 PRE Read Prefetching Enable If read prefetch is enabled, the PCI bridge
1 Read prefetching is
enabled.
prefetches 64 bytes from PCI memory in
response to a
PLB single-beat, byte-burst,
or
half word burst read from PMM O.
0 ENA PLB to PCI Memory Mapping Enable Note that PCILO_PMM2LA,
1 Memory mapping is enabled. PCILO_PMM2PCIHA, and
PCILO_PMM2PCILA must be initialized
before enabling.
17.5.2.11 PMM 2 PCI Low Address Register (PCILO_PMM2PCILA)
PCILO_PMM2PCILA defines the low-order 32 bits of the PCI address generated in response to a PLB
access
to range 2. See "PMM 0 PCI Low Address Register (PCILO_PMMOPCILA)" on page 17-22.
131
Figure 17-17. PMM 2 Low Address Register (PCILO_PMM2PCILA)
I 31:0 I PCI Low Address
17-26
PPC405GP User's Manual Preliminary