As
shown
in
Table
4-2,
tag
ways
A
and
B
store
data
address
bits A
O
:
19
for
each
line
in
cache
ways
A
and
B.
Data
address
bits
A
20
:
26
serve
as
the
index
to
the
cache
array.
The
two
cache
lines that
correspond
to
the
same
line
index
(one
in
each
way)
are
called
a congruence
class.
Table 4-2. Data Cache Organization
Tags (Two-way Set) Data (Two-way Set)
Way A
WayS
Way A
WayS
A
O
:
19
Line 0 A A
O
:
19
Line 0 S
Line 0 A Line 0 B
A
O
:
19
Line 1 A
A
O
:
19
Line 1 B
Line 1 A Line 1 B
·
·
· ·
·
·
·
·
·
· ·
·
A
O
:
19
Line 126 A A
O
:
19
Line 126 B Line 126 A Line 126 B
A
O
:
19
Line 127 A
A
O
:
19
Line 127 B
Line 127 A Line 127 B
When
a
cache
line
is
to
be
loaded,
the
cache
way
to
receive
the
line
is
determined
by
using
an
LRU
policy.
The
index,
determined
by
the
data
address,
selects a congruence
class.
Within a
congruence
class,
the
line
which
was
accessed
most recently
is
retained,
and
the
other
line
is
marked
as
LRU,
using
an
LRU
bit
in
the tag
array.
The
line
to
receive
the
incoming
data
is
the
LRU
line.
After
the
cache
line fill,
the
LRU
bit
is
then
set
to
identify
as
least-recently-used
the
line
opposite
the
line
just filled.
A
bypass
path
handles
data
operations
in
cache-inhibited memory
and
improves performance during
line
fill operations.
4.2.1
DCU
Operations
Data
from
cachable memory
regions
are
copied
from
external memory
into
lines
in
the
data
cache
array
so
that subsequent
cache
operations result
in
cache
hits.
Loads
and
stores that
hit
in
the
DCU
are
completed
in
one
cycle.
For
loads,
GPRs
receive
the
requested
byte,
halfword,
or
word
of
data
from
the
data cache
array.
The
DCU
supports byte-writeability
to
improve
the
performance
of
byte
and
halfword store operations.
Cache operations
require
a
line
fill
when
they require
data
from
cachable memory
regions
that
are
not
currently
in
the
DCU.
A
line
fill
is
the
movement
of
a
cache
line
(eight
words)
from
external memory
to
the
data
cache
array.
Eight
words
are
copied
from
external
memory
into
the
fill
buffer,
either target-
word-first
or
sequentially.
Loading
order
is
controlled
by
the
PLB
slave.
Target-word-first fills start
at
the requested
word,
continue
to
the
end
of
the
line,
and
then
wrap
to
fill
the
remaining
words
at
the
beginning
of
the
line.
Sequential fills start
at
the
first
word
of
the
cache
line
and
proceed sequentially
to
the
last
word
of
the
line.
In
both
types
of
fills,
the
fill
buffer,
when
full,
is
transferred
to
the
data
cache
array.
The
cache
line
is
marked
valid
when
it
is
filled.
Loads that result
in
a
line
fill,
and
loads
from
non-cachable
memory,
are
sent
to
a
GPR.
The
requested
byte,
halfword,
or
word
is
sent
from
the
DCU
to
the
GPR
from
the
fill
buffer,
using
a
cache
bypass mechanism. Additional loads
for
data
in
the
fill
buffer
can
be
bypassed
to
the
GPR
until
the
data
is
moved
into
the
data
array.
Stores
that
result
in
a
line
fill
have
their
dat~
held
in
the
fill
buffer
until
the
line
fill
completes.
Additional
stores
to
the
line
being
filled
will
also
have
their data
placed
in
the
fill buffer
before
being
transferred
into
the
data
cache
array.
4-6
PPC405GP User's Manual
Preliminary
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