IBM PowerPC 405GP User Manual

5
FIS FIT Interrupt Status
o No FIT interrupt is pending.
1
FIT interrupt is pending.
6:31
Reserved
11.5 Timer Control Register (TCR)
The TCR controls PIT, FIT, and watchdog timer operation.
The TCR[WRC]
field is cleared to 0 by all processor resets. (Chapter 8, "Reset and Initialization,"
describes the types of processor reset.) This field is set only by software. However, hardware does
not
allow software to clear the field after it is set. After software writes a 1 to a bit in the field, that bit
remains a 1
until any reset occurs. This prevents errant code from disabling the watchdog timer reset
function.
All processor resets clear TCR[ARE] to 0, disabling the auto-reload feature of the PIT.
WP WIE FP FIE
* + 4- 4-
31
1
f t t
WRC PIE ARE
Figure 11-7. Timer Control Register (TCR)
0:1
WP Watchdog Period
002
17
clocks
01 221 clocks
10 2
25
clocks
11 2
29
clocks
2:3
WRC Watchdog Reset Control
TCR[WRC] resets to 00.
00
No Watchdog reset will occur.
This field can be set
by software, but
01 Core reset will be forced by the cannot be cleared by software, except by a
Watchdog.
software-induced reset.
10 Chip reset will be forced by the
Watchdog.
11 System reset will be forced by the
Watchdog.,
4 WIE Watchdog Interrupt Enable
o Disable watchdog interrupt.
1 Enable watchdog interrupt.
5
PIE PIT Interrupt Enable
o Disable PIT interrupt.
1 Enable
PIT interrupt.
Preliminary
Timer Facilities
11-9

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English