IBM PowerPC 405GP

Table 17-9. PCI Configuration Address and Data Registers
Register
Address
Access Description
PCICO_CFGADDR
OxEECOOOOO
RIW
PCI Configuration Address Register
PCICO_CFGDATA
OxEECOOOO4
RIW
PCI Configuration Data Register
Table 17-10. PCI Configuration Register Offsets
Access
Register
Offset PLB PCI Description
PCICO_ VENDID
Ox01-0xOO
RIW
R PCI Vendor ID
PCICO_DEVID
Ox03-0x02 RIW
R PCI Device ID
PCICO_CMD
OxOS-ox04 RIW
RIW PCI Command Register
PCICO_STATUS
Ox07-ox06 RIW RIW
PCI Status
Register
PCICO_REVID
Ox08 RIW RIW PCI Revision ID
PCICO_PCICLS
OxOB-Ox09 RIW
R PCI Class Register
PCICO_CACHELS OxOC
R R PCI Cache Line Size
PCICO_LATTIM
OxOD RIW RIW PCI Latency Timer
PCICO_HDTYPE
OxOE
R R PCI Header Type
PCICO_BIST
OxOF R R PCI Built In Self Test Control
Reserved PCI BAR Ox13-0x10
R R Reserved, PCI BAR
PCICO_PTM1 BAR
Ox17-0x14
RIW RIW PCI PTM 1 BAR
PCICO_PTM2BAR
Ox1B-Ox18
RIW RIW PCI PTM 2 BAR
Reserved
PCI BAR
Ox1F-ox1C R R Reserved
PCI BAR. Refer to PCI Specification,
Version 2.2 for more information on
values.
Reserved PCI BAR Ox23-0x20
R R Reserved PCI BAR. Refer to PCI Specification,
Version 2.2 for more information on
values.
Reserved PCI BAR
Ox27-ox24 R R Reserved
PCI BAR. Refer to PCI Specification,
Version 2.2 for more information on
values.
Reserved Cardbus
Ox2B-Ox28
R
.R
Reserved Cardbus CIS Pointer. Refer to PCI
CIS Pointer
Specification, Version 2.2 for more information on
values.
PCICO_SBSYSVID
Ox2D-Ox2C RIW R
PCI Subsystem Vendor ID
PCICO_SBSYSID
Ox2F-Ox2E
RIW·
R
PCI Subsystem ID
Reserved Exp ROM
Ox33-0x30
R
R Reserved Expansion
ROM Base Address. Refer
Base Addr
to PCI Specification, Version 2.2 for more
information on
values.
PCICO_CAP
Ox34
R R PCI Capabilities Pointer
Reserved
Ox3B-Ox3S
R
R
Reserved
PCICO_INTLN
Ox3C
RIW RIW PCI Interrupt Line
PCICO_INTPN
Ox3D
R R PCI Interrupt Pin
PCICO_MINGNT
Ox3E
R R PCI Minimum Grant
PCICO_MAXLTNCY
Ox3F
R R
PCI Maximum Latency
PCICO_PCIICS Ox44
RIW
RIW
PCllnterrupt Control/Status
17-20
PPC40SGP User's Manual
Preliminary