IBM PowerPC 405GP User Manual

EVPR and the interrupt vector offset. (A user must initialize the EVPR contents at power-up using an
mtspr instruction.)
Table 10-4 shows the interrupt vector offsets for the interrupt types. Note that there can be multiple
sources of the same interrupt type; interrupts of the same type are mapped to the same interrupt
vector,
regardless of source. In such cases, the interrupt handling routine must examine status
registers to determine the exact source of the interrupt.
At the end of the interrupt
handling routine, execution of an rfi instruction forces the contents of SRRO
and SRR1 to be written to the program counter and the MSR, respectively. Execution then begins at
the address in the program counter.
Critical interrupts are processed similarly. When a critical interrupt is taken, Save/Restore
Register 2
(SRR2) and Save/Restore Register 3 (SRR3) hold the next sequential address to be
processed when returning from the interrupt, and the contents of the
MSR, respectively. At the end of
the
critical interrupt handling routine, execution of an rfci instruction writes the contents of SRR2 and
SRR3 into the program counter and the MSR, respectively.
Table 10-4.
Interrupt Vector Offsets
Offset Interrupt Type
Interrupt Class Category Page
Ox0100 Critical input interrupt
Asynchronous precise
Critical
10-34
Ox0200
Machine check-data
-
Critical
10-35
Machine check-instruction
-
Critical
10-35
Ox0300
Data storage interrupt- Synchronous precise Noncritical 10-36
MSR[DR]=1 and
ZPR[Zn] = 0 or
TLB_entry[WR] =
0 or
TLB_entry[UO] = 1 or
SUOR[Un] = 1
Ox0400
Instruction storage interrupt Synchronous precise
Noncritical
10-38
Ox0500
External
interrupt (external Asynchronous precise
Noncritical 10-38
to the processor core)
Ox0600 Alignment
Synchronous precise Noncritical 10-39
Ox0700
Program
Synchronous precise Noncritical 10-40
OxOCOO
Syste~ Call
Synchronous preCise Noncritical 10-41
Ox1000 PIT
Asynchronous precise Noncritical 10-41
Ox1010 FIT
Asynchronous precise Noncritical 10-42
Ox1020
Watchdog timer
Asynchronous precise Critical 10-43
Ox1100
Data TLB miss
Synchronous precise Noncritical 10-43
Ox1200 Instruction
TLB miss
Synchronous precise Noncritical 10-44
Ox2000
Debug-BT, DAC, DVC,
Synchronous precise
Critical
10-44
lAC,
IC, TIE
Debug-EXC, UDE Asynchronous precise
Critical
10.11 General Interrupt Handling Registers
The general interrupt handling registers are the Machine State Register (MSR), SRRO-SRR3, the
Exception Vector Prefix Register (EVPR), the Exception Syndrome Register
(ESR), and the Data
Exception Address Register (DEAR).
Preliminary
Interrupt Controller
Operations
10-27

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English