IBM PowerPC 405GP User Manual

16.7.4 Peripheral Bus Error Status Register 1 (EBCO_BESR1)
The Peripheral Bus Error Status Register 1 (EBCO_BESR1) records the occurrence and type of
errors for transactions attempted on
behalf of the MAL and DMA controllers. The contents of
EBCO_BESR1 are accessed indirectly through the EBCO_CFGADDR and EBCO_CFGDATA registers
using the
mfdcr and mtdcr instructions.
It is possible to have both a parity error and a bus error during the same data transfer. If this occurs
the bus error is detected first and
EBCO_BESR1 and EBCO_BEAR are updated. In the next cycle the
parity error is detected and, if error
locking is not enabled, logged in EBCO_BESR1.
EET5 FL5
+ +
10
3
1
1
t t
RWS5 AL5
Figure 16-20. Peripheral Bus Error Status Register 1 (EBCO_BESR1)
0:2 EET4 Error type for master 4
Master 4 is the MAL.
000 No error
001 Parity error
010 Reserved
011 Reserved
100 Protection error
101 Reserved
110 External bus input error
111 External bus timeout error
3
RWS4 Read/write status for master 4
o Error operation was a write operation
1 Error operation was a read operation
4 FL4
Field lock for master 4
o EET 4 and RWS4 fields are unlocked
1 EET 4 and RWS4 fields are locked
5 AL4
EBCO_BEAR address lock for master 4
o EBCO_BEAR address unlocked
1 EBCO_BEAR address locked
6:8 EET5 Error type for master 5
Master 5 is the DMA controller.
000
No error
001 Parity error
010 Reserved
011 Reserved
100 Protection error
101 Reserved
110 External bus input error
111 External bus timeout error
9
RWS5
Read/write status for master 5
o Error operation was a write operation
1 Error operation was a read operation
16-32
PPC405GP User's Manual

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English