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PowerPC 405GP
IBM PowerPC 405GP
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Table of Contents
Main Page
Table of Contents
6
Figures
30
About this Book
48
Who Should Use this Book
48
Conventions
49
Part I. Introducing the PPC405GP Embedded Processor
52
Chapter 1. Overview
54
PPC405GP Features
55
Bus and Peripheral Features
55
Figure 1-1. PPC405GP Block Diagram
55
Powerpc Processor Core Features
56
Powerpc Architecture
57
The PPC405GP as a Powerpc Implementation
58
RISC Processor Core Organization
58
Instruction and Data Cache Controllers
58
Instruction Cache Unit
59
Data Cache Unit
59
Memory Management Unit
59
Timer Facilities
61
Debug
61
Development Tool Support
61
Debug Modes
62
Processor Core Interfaces
62
Processor Local Bus
62
Device Control Register Bus
62
Clock and Power Management
62
Jtag
62
Interrupts
62
On-Chip Memory
62
Processor Core Programming Model
62
Data Types
63
Processor Core Register Set Summary
63
General Purpose Registers
63
Special Purpose Registers
63
Machine State Register
63
Condition Register
64
Device Control Registers
64
Chapter 2. On-Chip Buses
66
Processor Local Bus
66
PLB Features
67
PLB Masters and Slaves
67
PLB Master Assignments
67
Table 2-1. PPC405GP PLB Agents as Masters and Slaves
67
PLB Transfer Protocol
68
Table 2-2. Registers Controlling PLB Master Priority Assignments
68
Overlapped PLB Transfers
69
Figure 2-1. Overlapped PLB Transfers
69
PLB Arbiter Registers
70
PLB Arbiter Control Register (PLBO_ACR)
70
PLB Error Address Register (PLBO_BEAR)
70
Table 5-1
70
PLB Error Status Register (PLBO_BESR)
71
PLB to OPB Bridge Registers
73
Bridge Error Address Register (POBO_BEAR)
73
Bridge Error Status Registers (POBO_BESRO-POBO_BESR1)
73
Table 2-4. PLB Arbiter Registers
73
On-Chip Peripheral Bus
76
OPB Features
76
OPB Master Assignments
77
OPB Arbiter Registers
77
OPB Arbiter Control Register (OPBAO_CR)
77
Table 2-6. PLB Arbiter Registers
77
OPB Arbiter Priority Register (OPBAO_PR)
78
Part II. the PPC405GP Rise Processor
80
Chapter 3. Programming Model
82
User and Privileged Programming Models
82
Memory Organization and Addressing
82
Physical Address Map
83
Table 3-1. PPC405GP Address Space
83
Storage Attributes
84
Registers
84
Figure 3-1. PPC405GP Programming Model-Registers
86
General Purpose Registers (RO-R31)
87
Special Purpose Registers
87
Figure 3-2. General Purpose Registers (RO-R31)
87
Count Register (CTR)
88
Link Register (LR)
89
Fixed Point Exception Register (XER)
89
Figure 3-3. Count Register (CTR)
89
Figure 3-4. Link Register (LR)
89
Figure 3-5. Fixed Point Exception Register (XER)
91
Table 3-3. XER[CA] Updating Instructions
91
Special Purpose Register General (SPRGO-SPRG7)
92
Table 3-4. XER[SO,OV] Updating Instructions
92
Processor Version Register (PVR)
93
Condition Register (CR)
93
Figure 3-7. Processor Version Register (PVR)
93
CR Fields after Compare Instructions
94
Figure 3-8. Condition Register (CR)
94
The CRO Field
95
The Time Base
96
Machine State Register (MSR)
96
Figure 3-9. Machine State Register (MSR)
96
Table 3-5. Time Base Registers
96
Device Control Registers
97
Directly Accessed Dcrs
98
Figure 7-3. Chip Control Register
98
Table 3-6. Directly Accessed Dcrs
98
Indirectly Accessed Dcrs
100
Indirect Access of SDRAM Controller Dcrs
100
Table 3-7. SDRAM Controller DCR Usage
100
Table 3-8. Offsets for SDRAM Controller Registers
100
Indirect Access of External Bus Controller Dcrs
101
Table 3-9. External Bus Controller DCR Usage
101
Table 3-10. Offsets for External Bus Controller Registers
101
Indirect Access of Decompression Controller Dcrs
102
Table 3-11. Decompression Controller DCR Usage
102
Table 3-12. Offsets for Decompression Controller Registers
102
Memory-Mapped Input/Output Registers
103
Directly Accessed MMIO Registers
103
Table 3-13. Directly Accessed MMIO Registers
103
Figure 19-15. Mode Register
105
Indirectly Accessed MMIO Registers
106
Table 3-15. PCI Configuration Registers
106
Data Types and Alignment
107
Figure 3-10. PPC405GP Data Types
107
Alignment for Storage Reference and Cache Control Instructions
108
Alignment and Endian Operation
108
Summary of Instructions Causing Alignment Exceptions
109
Byte Ordering
109
Table 3-16. Alignment Exception Summary
109
Structure Mapping Examples
110
Big Endian Mapping
110
Little Endian Mapping
111
Support for Little Endian Byte Ordering
111
Endian (E) Storage Attribute
111
Fetching Instructions from Little Endian Storage Regions
112
Accessing Data in Little Endian Storage Regions
112
Powerpc Byte-Reverse Instructions
113
Figure 3-11. Normal Word Load or Store (Big Endian Storage Region)
113
Figure 3-12. Byte-Reverse Word Load or Store (Little Endian Storage Region)
113
Instruction Processing
114
Figure 3-13. Byte-Reverse Word Load or Store (Big Endian Storage Region)
114
Figure 3-14. Normal Word Load or Store (Little Endian Storage Region)
114
Branch Processing
115
Unconditional Branch Target Addressing Options
115
Conditional Branch Target Addressing Options
116
Conditional Branch Condition Register Testing
116
BO Field on Conditional Branches
116
Table 3-17. Bits of the BO Field
116
Branch Prediction
117
Table 3-18. Conditional Branch BO Field
117
Speculative Accesses
118
Speculative Accesses in the PPC405GP
118
Prefetch Distance down an Unresolved Branch Path
119
Prefetch of Branches to the CTR and Branches to the LR
119
Preventing Inappropriate Speculative Accesses
119
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction
120
Fetching Past Tw or Twi Instructions
120
Fetching Past an Unconditional Branch
121
Suggested Locations of Memory-Mapped Hardware
121
Table 3-19. Example Memory Mapping
121
Privileged Mode Operation
122
MSR Bits and Exception Handling
122
Privileged Instructions
123
Privileged Sprs
123
Privileged Dcrs
124
Synchronization
124
Context Synchronization
125
Executio!,,! Synchronization
127
Storage Synchronization
127
Instruction Set
128
Table 3-21. PPC405GP Instruction Set Summary
128
Instructions Specific to IBM Powerpc Embedded Processors
129
Storage Reference Instructions
129
Table 3-22. Implementation-Specific Instructions
129
Table 3-23. Storage Reference Instructions
129
Arithmetic Instructions
130
Table 3-24. Arithmetic Instructions
130
Logical Instructions
131
Compare Instructions
131
Table 3-25. Multiply-Accumulate and Multiply Halfword Instructions
131
Table 3-26. Logical Instructions
131
Table 3-27. Compare Instructions
131
Branch Instructions
132
CR Logical Instructions
132
Rotate Instructions
132
Table 3-28. Branch Instructions
132
Table 3-29. CR Logical Instructions
132
Table 3-30. Rotate Instructions
132
Shift Instructions
133
Cache Management Instructions
133
Interrupt Control Instructions
133
Table 3-31. Shift Instructions
133
Table 3-32. Cache Management Instructions
133
Table 3-33. Interrupt Control Instructions
133
TLB Management Instructions
134
Processor Management Instructions
134
Extended Mnemonics
134
Table 3-34. TLB Management Instructions
134
Table 3-35. Processor Management Instructions
134
Chapter 4. Cache Operations
136
ICU Organization
136
Table 4-1. Instruction Cache Organization
137
Figure 4-1. Instruction Flow
138
Instruction Cachability Control
139
Instruction Cache Synonyms
139
ICU Coherency
140
DCU Organization
140
DCU Operations
141
Table 4-2. Data Cache Organization
141
DCU Write Strategies
142
DCU Load and Store Strategies
142
Data Cachability Control
143
DCU Coherency
144
Cache Instructions
144
ICU Instructions
144
DCU Instructions
145
Cache Control and Debugging Features
146
Figure 4-2. Core Configuration Register
146
CCRO Programming Guidelines
148
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR)
149
DCU Debugging
150
DCU Performance
151
Pipeline Stalls
151
Cache Operation Priorities
152
Table 4-3. Priority Changes with Different Data Cache Operations
152
Simultaneous Cache Operations
153
Sequential Cache Operations
153
Chapter 5. On-Chip Memory
154
OCM Programming Guidelines
155
Store Data Bypass Behavior and Memory Coherency
156
Registers
158
Table 5-2. OCM Dcrs
158
OCM Instruction-Side Control Register (OCMO_ISCNTL)
159
OCM Data-Side Address Range Compare Register (OCMO_DSARC)
159
Chapter 6. Memory Management
162
MMU Overview
162
Address Translation
162
Translation Lookaside Buffer (TLB)
163
Unified TLB
163
Figure 6-1. Effective to Real Address Translation Flow
163
TLB Fields
164
Page Identification Fields
164
Translation Field
165
Table 6·1. TLB Fields Related to Page Size
165
Access Control Fields
166
Storage Attribute Fields
166
Shadow Instruction TLB
167
ITLB Accesses
167
Shadow Data TLB
168
DTLB Accesses
168
Shadow TLB Consistency
169
Figure 6-3. ITLB/DTLB/UTLB Address Resolution
169
TLB-Related Interrupts
170
Data Storage Interrupt
170
Instruction Storage Interrupt
170
Data TLB Miss Interrupt
170
Instruction TLB Miss Interrupt
170
TLB Management
171
TLB Search Instructions (Tlbsxltlbsx.)
172
TLB Invalidate Instruction (Tibia)
172
TLB Sync Instruction (Tlbsync)
172
Recording Page References and Changes
172
Access Protection
173
Access Protection Mechanisms in the TLB
173
General Access Protection
173
Execute Permissions
174
Write Permissions
174
Zone Protection
174
Figure 6-5. Zone Protection Register (ZPR)
175
Access Protection for Cache Control Instructions
176
Table 6-2. Protection Applied to Cache Control Instructions
176
Access Protection for String Instructions
177
Real-Mode Storage Attribute Control
178
Storage Attribute Control Registers
179
Data Cache Write-Through Register (DCWR)
179
Figure 6-6. Generic Storage Attribute Control Register
179
Data Cache Cachability Register (DCCR)
180
Instruction Cache Cachability Register (ICCR)
180
Storage Guarded Register (SGR)
180
Storage User-Defined 0 Register (SUOR)
180
Part III. PPC405GP System Operations
182
Chapter 7. Clocking
184
PLL Overview
184
Figure 7-1. PPC405GP Clocking
184
Input Reference Clock (Sysclk)
185
External Clock Strapping Setup
186
Table 7-1. Clock Strapping Values
186
Sample Clock Ratios
187
Table 7-2. PLL Tuning Settings
187
Table 7-3. Possible Clocking Ratios for Reference Clock of 33.3Mhz
188
Table 7-4. Possible Clocking Ratios for Reference Clock of 25Mhz
189
PCI Clocking
190
PCI Clocks
191
PCI Adapter Applications
191
Table 7-6. Example Synchronous PCI Clock Frequencies in Asynchronous Mode
191
Serial Port Clocking
192
Clocking Registers
192
Table 7-7. Clocking Control Registers
192
PLL Mode Register (CPCO_PLLMR)
193
Chip Control Register 0 (CPCO_CRO)
195
Reset and Initialization
198
Reset Signals
198
Reset Types
198
Core Reset
198
Chip Reset
198
System Reset
199
PCI Power Management Initiated Resets
199
Processor Initiated Resets
199
Processor State after Reset
199
Processor Register Contents after Reset
200
Machine State Register Contents after Reset
200
Table 8-1. MSR Contents after Reset
200
Contents of Special Purpose Registers after Reset
201
OCR Contents after Reset
201
Table 8-2. SPR Contents after Reset
201
Table 8-3. DCR Contents after Reset
201
MMIO Register Contents after Reset
205
Table 8-4. MMIO Register Contents after Reset
205
PPC405GP Chip Initialization
209
OCM Initialization
210
Initializing Instruction-Side OCM
210
Initializing Data-Side OCM
210
UIC Initialization
211
UART Initialization
211
PPC405GP Initial Processor Sequencing
211
Initialization Requirements
212
Initialization Code Example
213
Chapter 9. Pin Strapping and Sharing
216
Pin Strapping
216
Pin Sharing
218
Table 9-1. Multiplexed Pins
218
Chapter 10. Interrupt Controller Operations
220
UIC Overview
220
UIC Features
220
UIC Interrupt Assignments
220
Table 10-1. UIC Interrupt Assignments
220
Interrupt Programmability
222
UIC Status Register (UICO_SR)
222
Table 10-2. UIC Dcrs
222
UIC Enable Register (UICO_ER)
225
UIC Critical Register (UICO_CR)
227
UIC Polarity Register (UICO_PR)
229
UIC Trigger Register (UICO_TR)
232
UIC Masked Status Register (UICO_MSR)
235
UIC Vector Configuration Register (UICO_VCR)
237
UIC Vector Register (UICO_VR)
238
Using the Value in UICO_VR as a Vector Address or Entry Table Lookup
239
Vector Generation Scenarios
239
Interrupt Handling in the Processor Core
241
Architectural Definitions and Behavior
241
Behavior of the PPC405GP Implementation
242
Interrupt Handling Priorities
243
Table 10-3. Interrupt Handling Priorities
244
Critical and Noncritical Interrupts
245
General Interrupt Handling Registers
246
Table 10-4. Interrupt Vector Offsets
246
Machine State Register (MSR)
247
Figure 10-9. Machine State Register (MSR)
247
Save/Restore Registers 0 and 1 (SRRO-SRR1)
248
Figure 10-10. Save/Restore Register 0 (SRRO)
248
Save/Restore Registers 2 and 3 (SRR2-SRR3)
249
Figure 10-11. Save/Restore Register 1 (SRR1)
249
Figure 10-12. Save/Restore Register 2 (SRR2)
249
Exception Vector Prefix Register (EVPR)
250
Exception Syndrome Register (ESR)
250
Figure 10-13. Save/Restore Register 3 (SRR3)
250
Figure 10-14. Exception Vector Prefix Register (EVPR)
250
Figure 10-15. Exception Syndrome Register (ESR)
251
Table 10-5. ESR Alteration by Various Interrupts
252
Table 10-6. ESR Alteration by Various Interrupts
252
Data Exception Address Register (DEAR)
253
Critical Input Interrupts
253
Figure 10-16. Data Exception Address Register (DEAR)
253
Machine Check Interrupts
254
Instruction Machine Check Handling
254
Table 10-7. Register Settings During Critical Input Interrupts
254
Data Machine Check Handling
255
Data Storage Interrupt
255
Table 10-8. Register Settings During Machine Check-Instruction Interrupts
255
Table 10-9. Register Settings During Machine Check-Data Interrupts
255
Table 10-10. Register Settings During Data Storage Interrupts
256
Instruction Storage Interrupt
257
External Interrupt
257
Table 10-11. Register Settings During Instruction Storage Interrupts
257
External Interrupt Handling
258
Alignment Interrupt
258
Table 10-12. Register Settings During External Interrupts
258
Table 10-13. Alignment Interrupt Summary
258
Program Interrupt
259
Table 10-14. Register Settings During Alignment Interrupts
259
Table 10-15. ESR Usage for Program Interrupts
259
System Call Interrupt
260
Programmable Interval Timer (PIT) Interrupt
260
Table 10-16. Register Settings During Program Interrupts
260
Table 10-17. Register Settings During System Call Interrupts
260
Fixed Interval Timer (FIT) Interrupt
261
Table 10-18. Register Settings During Programmable Interval Timer Interrupts
261
Table 10-19. Register Settings During Fixed Interval Timer Interrupts
261
Watchdog Timer Interrupt
262
Data TLB Miss Interrupt
262
Table 10-20. Register Settings During Watchdog Timer Interrupts
262
Table 10-21. Register Settings During Data TLB Miss Interrupts
262
Instruction TLB Miss Interrupt
263
Debug Interrupt
263
Table 10-22. Register Settings During Instruction TLB Miss Interrupts
263
Table 10-23. SRR2 During Debug Interrupts
264
Table 10-24. Register Settings During Debug Interrupts
264
Chapter 11. Timer Facilities
266
Figure 11-1. Relationship of Timer Facilities to the Time Base
266
Time Base
267
Figure 11-2. Time Base Lower (TBL)
267
Reading the Time Base
268
Writing the Time Base
268
Figure 11-3. Time Base Upper (TBU)
268
Table 11-1. Time Base Access
268
Programmable Interval Timer (PIT)
269
Fixed Interval Timer (FIT)
270
Figure 11-4. Programmable Interval Timer (PIT)
270
Table 11-2. FIT Controls
270
Watchdog Timer
271
Table 11-3. Watchdog Timer Controls
271
Figure 11-5. Watchdog Timer State Machine
272
Timer Status Register (TSR)
273
Figure 11-6. Timer Status Register (TSR)
273
Timer Control Register (TCR)
274
Figure 11-7. Timer Control Register (TCR)
274
Chapter 12. Debugging
276
Development Tool Support
276
Debug Interfaces
276
IEEE 1149.1 Test Access Port (JTAG Debug Port)
276
JTAG Connector
277
JTAG Instructions
278
JTAG Boundary Scan
278
Table 12-2. JTAG Instructions
278
JTAG Implementation
279
Trace Port
280
Figure 12-3. Risctrace Header (Top View)
280
Table 12-3. Risctrace Header Pin Description
280
Debug Modes
281
Internal Debug Mode
281
External Debug Mode
281
Debug Wait Mode
282
Real-Time Trace Debug Mode
282
Processor Control
283
Processor Status
283
Debug Registers
283
Debug Control Registers
284
Debug Control Register
284
Figure 12-4. Debug Control Register 0 (DBCRO)
284
Debug Control Register1 (DBCR1)
286
Figure 12-5. Debug Control Register 1 (DBCR1)
286
Debug Status Register (DBSR)
287
Instruction Address Compare Registers (IAC1-IAC4)
289
Data Address Compare Registers (DAC1-DAC2)
289
Figure 12-7. Instruction Address Compare Registers (IAC1-IAC4)
289
Data Value Compare Registers (DVC1-DVC2)
290
Figure 12-8. Data Address Compare Registers (DAC1-DAC2)
290
Figure 12-9. Data Value Compare Registers (DVC1-DVC2)
290
Debug Events
291
Branch Taken Debug Event
292
Exception Taken Debug Event
292
Trap Taken Debug Event
292
Unconditional Debug Event
292
Lac Debug Event
292
Lac Exact Address Compare
292
Lac Range Address Compare
292
Figure 12-10. Inclusive Lac Range Address Compares
293
Figure 12-11. Exclusive Lac Range Address Compares
293
DAC Debug Event
294
DAC Exact Address Compare
294
DAC Range Address Compare
294
Data Address Compare (DAC) Applied to Cache Instructions
295
Figure 12-12. Inclusive DAC Range Address Compares
295
Figure 12-13. Exclusive DAC Range Address Compares
295
Data Value Compare Debug Event
296
Table 12-7. Comparisons Based on Dbcr1[Dvnm]
298
Chapter 13. Clock and Power Management
300
CPM Registers
300
Table 13-1. CPM Registers
300
Chapter 14. Decompression Controller Operation
304
Code Compression
304
Code Decompression
305
Instruction Fetches to Compressed
305
Instruction Fetches to Uncompressed
306
Performance
306
Decompression Controller Registers
306
Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3)
307
Table 14-1. Dcrs Used to Access the Decompression Controller Registers
307
Table 14-2. Offsets for Decompression Controller Registers
307
Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1)
308
Decompression Configuration Register (DCPO_CFG)
308
Decompression Controller ID Register (DCPO_ID)
309
Decompression Controller Error Status Register (DCPO_ESR)
310
Part IV. PPC405GP External Interfaces
314
Chapter 15. SDRAM Controller
316
Interface Signals
316
Figure 15-1. SDRAM Controller Signals
316
Table 15-1. SDRAM Signal Usage and State During/Following Reset
317
Table 15-5. SDRAM
318
Memory Controller Status (SDRAMO_STATUS)
320
Memory Bank 0-3 Configuration (SDRAMO_BOCR-SDRAMO_B3CR)
321
Page Management
322
Logical Address to Memory Address Mapping
323
Table 15-6. Logical Address Bit on BA 1:0 and Memaddr12:0 Versus Addressing Mode
323
SDRAM Timing Register (SDRAMO_ TR)
324
Selected Timing Diagrams
325
Table 15-7. SDRAM Memory Timing Parameters
325
Figure 15-6. Activate, Four Word Read, Precharge, Activate
326
Figure 15-7. Activate, Four Word Write, Precharge, Activate
326
Figure 15-8. Precharge All, Activate
327
Figure 15-9. CAS before RAS Refresh
327
Auto (CAS before RAS) Refresh
328
Refresh Timer Register (SDRAMO_RTR)
328
Error Checking and Correction (ECC)
329
ECC Configuration Register (SDRAMO_ECCCFG)
329
Table 15-8. Additional Latency When Using ECC
329
Correctable ECC Errors
330
Uncorrectable ECC Errors
330
Error Locking
331
ECC Error Status Register (SDRAMO_ECCESR)
331
Bus Error Address Register (SDRAMO_BEAR)
332
Bus Error Syndrome Register (SDRAMO_BESRO)
332
Bus Error Syndrome Register 1 (SDRAMO_BESR1)
333
Self-Refresh
334
Power Management
335
Sleep Mode Entry
335
Power Management Idle Timer (SDRAMO_PMIT)
335
Sleep Mode Exit
336
Chapter 16. External Bus Controller
338
Interface Signals
338
Figure 16-1. External Bus Controller Signals
339
Table 16-1. EBC Signal Usage and State During/Following a Chip or System Reset
339
Interfacing to Byte, Halfword and Word Devices
340
Multiplexed Ii0S
341
Driver Enables
341
Non-Burst Peripheral Bus Transactions
342
Table 16-2. Effect of Driver Enable Programming on EBC Signal States
342
Single Read Transfer
343
Figure 16-3. Single Read Transfer
343
Single Write Transfer
344
Figure 16-4. Single Write Transfer
344
Burst Transactions
345
Burst Read Transfer
346
Figure 16-5. Burst Read Transfer
346
Burst Write Transfer
347
Figure 16-6. Burst Write Transfer
347
Device-Paced Transfers
348
Device-Paced Single Read Transfer
349
Figure 16-7. Device-Paced Single Read Transfer
349
Device-Paced Single Write Transfer
350
Figure 16-8. Device-Paced Single Write Transfer
350
Device-Paced Burst Read Transfer
351
Figure 16-9. Device-Paced Burst Read Transfer
351
Device-Paced Burst Write Transfer
352
Figure 16-10. Device-Paced Burst Write Transfer
353
External Bus Master Interface
354
Arbitration
354
Table 16-3. External Master Arbitration
355
Table 16-4. Signal States During Hold Acknowledge (Holdack=1)
355
Transaction Overview
356
Single Read and Single Write Transfers
356
Burst Read Transfer
357
Figure 16-12. External Master Arbitration, Single Read and Single Write
357
Burst Write Transfer
358
Figure 16-13. External Master Burst Read
358
External Master Error Interrupts
359
Figure 16-14. External Master Burst Write
359
EBC Registers
360
Table 16-5. EBC DCR Addresses
360
Table 16-6. External Bus Configuration and Status Registers
360
Peripheral Bank Configuration Registers (Ebco_Bncr)
362
Peripheral Bank Access Parameters (Ebco_Bnap)
363
Error Reporting
366
Error Locking
366
Peripheral Bus Error Address Register (EBCO_BEAR)
366
Peripheral Bus Error Status Register (EBCO_BESRO)
367
Peripheral Bus Error Status Register 1 (EBCO_BESR1)
369
PCI Overview
372
PCI Bridge Features
372
PCI Bridge Block Diagram
373
Byte Ordering
373
Figure 17-1. PCI Bridge Block Diagram
373
Reference Information
374
Table 17-1. Powerpc, Coreconnect PLB, and PCI Address Bit-Naming Conventions
374
Table 17-2. Powerpc, Coreconnect PLB, and PCI Data Bus Bit-Naming Conventions
374
PCI Bridge Functional Blocks
375
PLB-To-PCI Half-Bridge
375
Figure 17-2. PLB-To-PCI Half-Bridge Block Diagram
375
PCI-To-PLB Half-Bridge
376
PCI Arbiter
376
Figure 17-3. PCI-To-PLB Half-Bridge Block Diagram
376
Figure 17-4. Arbitration Structure
376
PLB-To-PCI Address Mapping
377
Table 17-3. PLB Address Map
377
PCI-To-PLB Address Mapping
379
Figure 17-5. PMM Register Sets Map PLB Address Space to PCI Address Space
379
Table 17-4. PCI Memory Address Map
379
PCI Target Map Configuration
380
Figure 17-6. PTM Register Sets Map PCI Address Space to PLB Address Space
380
PCI Bridge Transaction Handling
381
PLB-To-PCI Transaction Handling
381
PCI Master Commands
381
PLB Slave Read Handling
383
Prefetching
383
PLB Slave Write Handling
383
Aborted PLB Requests
384
Retried PCI Reads
384
PCI-To-PLB Transaction Handling
384
PLB Master Commands
385
Handling of Reads from PCI Masters
386
Handling Writes from PCI Masters
388
Miscellaneous
388
Completion Ordering
389
PCI Producer-Consumer Model
389
Collision Resolution
389
PCI Bridge Configuration Registers
390
PCI Bridge Register Summary
390
Table 17-7. Collision Resolution
390
Table 17-9. PCI Configuration Address and Data Registers
391
Table 17-10. PCI Configuration Register Offsets
391
PCI Bridge Local Configuration Registers
392
PMM 1 Mask/Attribute Register (PCILO_PMM1MA)
395
PMM 1 PCI Low Address Register (PCILO_PMM1PCILA)
395
Figure 17-10. PMM 0 High Address Register (PCILO_PMMOPCIHA)
396
PCI Configuration Registers
400
PCI Configuration Address Register (PCICO_CFGADDR)
400
PCI Configuration Data Register (PCICO_CFGDATA)
401
PCI Latency Timer Register (PCICO_LATTIM)
407
PCI Header Type Register (PCICO_HDTYPE)
407
Unused PCI Base Address Register Space
408
Pcllnterrupt Control/Status Register (PCICO_ICS)
413
Error Enable Register (PCICO_ERREN)
413
Error Status Register (PCICO_ERRSTS)
414
Bridge Options 1 Register (PCICO_BRDGOPT1)
415
(Pcico_Plbbesro)
418
PLB Slave Error Syndrome Register 1 (PCICO_PLBBESR1)
418
PLB Slave Error Address Register (PCICO_PLBBEAR)
419
Power Management Capabilities (PCICO_PMC)
421
Power Management Control/Status Register (PCICO_PMCSR)
421
PMCSR PCI-To-PCI Bridge Support Extensions (PCICO_PMCSRBSE)
422
PCI Data Register (PCICO_DATA)
423
Bridge Options 2 Register (PCICO_BRDGOPT2)
423
Power Management State Change Request Register (PCICO_PMSCRR)
425
Error Handling
426
PLB Unsupported Transfer Type
426
PCI Master Abort
426
Bridge PCI Master Receives Target Abort While PCI Bus Master
427
PCI Target Data Bus Parity Error Detection
428
PCI Master Data Bus Parity Error Detection
428
PCI Address Bus Parity Error While PCI Target
429
PLB Master Bus Error Detection
429
PCI Bridge Clocking Configuration
430
PCI Power Management Interface
430
Capabilities and Power Management Status and Control Registers
430
Power State Control
430
Changing Power States
431
Address Map Initialization
432
Other Configuration Register Initialization
434
Table 17-12. Address Map Register Values
434
Local Processor Boot from PCI Memory
435
Configuration Cycles for Other Devices
435
Timing Diagrams
435
PCI Master Burst Read from SDRAM
436
PCI Master Burst Write to SDRAM
436
CPU Read from PCI Memory Slave, Nonprefetching
436
CPU Read from PCI Memory Slave, Prefetching
436
CPU Write to PCI Memory Slave
436
PCI Memory to SDRAM DMA Transfer
437
SDRAM to PCI Memory DMA Transfer
437
Asynchronous
437
Figure 17-60. PCI Master Burst Read from SDRAM
439
Figure 17-61. PCI Master Burst Write to SDRAM
443
Figure 17-62. CPU Read from PCI Memory Slave, Nonprefetching
447
Figure 17-63. CPU Read from PCI Memory Slave, Prefetching
450
Figure 17-64. CPU Write to PCI Memory Slave
453
Figure 17-65. PCI Memory to SDRAM DMA Transfer
457
Figure 17-66. SDRAM to PCI Memory DMA Transfer
460
Synchronous
463
Figure 17-67. PCI Master Burst Read from SDRAM
463
Figure 17-68. PCI Master Burst Write to SDRAM
471
Figure 17-69. CPU Read from PCI Memory Slave, Nonprefetching
477
Figure 17-70. CPU Read from PCI Memory Slave, Prefetching
479
Figure 17-71. CPU Write to PCI Memory Slave
483
Figure 17-72. PCI Memory to SDRAM DMA Transfer
487
Figure 17-73. SDRAM to PCI Memory DMA Transfer
491
Chapter 18. Direct Memory Access Controller
494
External Interface Signals
494
Functional Overview
495
Peripheral Mode Transfers
495
Figure 18-1. DMA Controller External Bus Control Signals
495
Memory-To-Memory Transfers
496
Scatter/Gather Transfers
497
Configuration and Status Registers
497
Table 18-2. DMA Controller Configuration and Status Registers
497
DMA Polarity Configuration Register (DMAO_POL)
498
DMA Sleep Mode Register (DMAO_SLP)
499
DMA Status Register (DMAO_SR)
500
DMA Channel Control Registers (DMAO_CRO-DMAO_CR3)
501
DMA Source Address Registers (DMAO_SAO-DMAO_SA3)
503
DMA Destination Address Registers (DMAO_DAO-DMAO_DA3)
504
DMA Count Registers (DMAO_CTO-DMAO_CT3)
504
DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-DMAO_SG3)
505
DMA Scatter/Gather Command Register (DMAO_SGC)
506
Channel Priorities
506
Data Parity During DMA Peripheral Transfers
507
Errors
507
Address Alignment Error
507
Table 18-3. DMA Transfer Priorities
507
PLB Timeout
508
Slave Errors
508
DMA Interrupts
508
Table 18-4. Address Alignment Requirements
508
Scatter/Gather Transfers
509
Table 18-5. Scatter/Gather Descriptor Table
509
Table 18-6. Bit Fields in the Scatter/Gather Descriptor Table
509
Programming the DMA Controller
510
Peripheral Mode Transfers
510
Table 18-7. DMA Registers Loaded from Scatter/Gather Descriptor Table
510
Figure 18-12. Memory to Peripheral DMA Transfer
512
Memory-To-Memory Transfers
513
Software-Initiated Memory-To-Memory Transfers (Non-Deviced Paced)
514
Chapter 19. Ethernet Media Access Controller
516
EMAC Features
517
Figure 19-1. EMAC in a Typical Ethernet Application
517
EMAC Operation
518
Figure 19-2. Internal EMAC Structure
518
MAL Slave Logic
519
OPB Slave Logic
519
Ethernet Address Match Logic
519
Configuration and Status Registers
519
Wake on LAN Logic
519
Ethernet MAC
520
EMAC Loop-Back Modes
520
EMAC Transmit Operation
520
Figure 19-3. EMAC Loop-Back Modes
520
Arbitration between TX Channels
521
Independent Mode
521
Dependent Mode
521
MAL TX Descriptor Control/Status Field
522
Figure 19-4. MAL TX Descriptor Control/Status Field
522
Early Packet Termination in Transmit
524
Empty Packets
524
Automatic Retransmission of Collided Packets
524
Inter-Packet Gap (IPG) Tuning
524
Full-Duplex Operation
524
Figure 19-5. Transmit Packet Structure (Excluding VLAN Tagged and Control Packets)
525
Table 19-1. FCS/SA Enable - Possible Configurations
526
Table 19-2. Fcs/Pad Enable - Possible Configurations
526
Table 19-3. FCSNLAN Tag Enable - Possible Configurations
526
Figure 19-6. MAL RX Descriptor Control/Status Field
527
Table 19-4. in Range Length Error Behavior for Various Packet Lengths
528
Figure 19-7. Wake-Up Packet Format
529
Figure 19-8. Control Packet Format
531
Figure 19-9. Integrated Flow Control Mechanism
532
Figure 19-10. Pause Operation State Machine
533
Figure 19-11. Tagged MAC Packet Format
534
Figure 19-12. Tag Control Information Field Structure
534
Figure 19-13. Receive Address Recognition Flowchart
537
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