Programming
Note: MSR[EE] also enables PIT and FIT interrupts. However, after timer
interrupts, control passes to different interrupt vectors than for the interrupts discussed in the
preceding paragraph. Therefore, these timer interrupts are described
in
"Programmable Interval
Timer (PIT) Interrupt" on page 10-41 and "Fixed Interval Timer (FIT) Interrupt" on page 10-42.
10.16.1 External Interrupt Handling
When MSR[EE] = 1 (external interrupts are enabled), a noncritical external interrupt occurs, and this
interrupt is the highest priority interrupt condition, the processor immediately writes the address of the
next sequential instruction into
SRRO.
Simultaneously, the contents of the MSR are saved in SRR1.
When the processor takes a noncritical external interrupt, MSR[EE] is set to
o.
This disables other
external interrupts from interrupting the interrupt handler before
SRRO
and
SRR1
are saved. The
MSR is also written with the other values shown
in
Table 10-12, "Register Settings during External
Interrupts," on page 10-39. The high-order 16 bits of the program counter are written with the contents
of the EVPR and the low-order 16 bits of the program counter are written with
Ox0500. Interrupt
processing begins at the address
in
the program counter.
Executing an rfi instruction restores the program counter from
SRRO
and the MSR from SRR1, and
execution resumes at the address in the program counter.
Table 10-12.
Register
Settings
during
External
Interrupts
SRRO
Written with the address of the next sequential instruction
SRR1
Written with the contents of the MSR
MSR
WE, EE, PR,
OWE,
IR,
DR
f-
0
CE, ME, DE
f-
unchanged
PC
EVPR[O:15]
II
Ox0500
10.17 Alignment Interrupt
Alignment interrupts are caused by
dcbz
instructions to non-cachable or write-through storage and.
Table
10-13 summarizes the instructions and conditions causing alignment interrupts.
Table 10-13.
Alignment
Interrupt
Summary
Instructions
Causing
Alignment
Interrupts
Conditions
dcbz
EA in non-cachable or write-through storage
dcread,
Iwarx,
stwcx.
EA not word-aligned
Execution of
an
instruction causing an alignment interrupt is prohibited from completing.
SRRO
is
written with the address of that instruction and the current contents of the
MSR are saved into SRR1.
The DEAR is written with the address that caused the alignment error. The MSR bits are written with
the values shown
in
Table 10-14, "Register Settings during Alignment Interrupts," on page 10-40. The
high-order 16 bits of the program counter are written with the contents of the
EVPR and the low-order
16 bits of the program counter are written with
Ox0600. Interrupt processing begins at the new
address
in
the program counter.
Preliminary Interrupt Controller Operations 10-39
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