Iwz
Iwz
Ii
mttbl
mttbu
mttbl
Rx,
upper
Ry,
lower
Rz,O
Rz
Rx
Ry
# load 64-bit time base value into
Rx
and
Ry
# force
TBL
to 0 to avoid rollover while writing TBU
#set
TBU
# set
TBL
11.2 Programmable Interval Timer (PIT)
The PIT is a 32-bit SPR that decrements at the same rate as the time base. The PIT is read and
written using
mfspr
and mtspr, respectively. Writing to the PIT also simultaneously writes to a hidden
reload register. Reading the
PIT using
mfspr
returns the current PIT contents; the hidden reload
register cannot be read. When a non-zero
value is written to the
PIT,
it begins to
decrement
A PIT
event occurs when a decrement occurs on a PIT count of
1.
When a PIT event occurs, the following
occurs:
1.
If the PIT is
in
auto-reload mode (the ARE field of the Timer Control Register (TCR) is 1), the PIT is
loaded with the
last value an
mtspr
wrote to the
PIT.
A decrement from a PIT count of 1
immediately causes a reload; no intermediate
PIT content of 0 occurs.
If the PIT is not
in
auto-reload mode (TCR[ARE] = 0), a decrement from a PIT count of 1 simply
causes a
PIT content of
O.
2. TSR[PIS] is set to
1.
3.
If enabled (TCR[PIE] = 1 and the EE field of the Machine State Register (MSR) is 1), a PIT
interrupt is taken. See "Programmable Interval Timer (PIT) Interrupt" on page 10-41 for details of
register behavior during a
PIT interrupt.
The interrupt handler should use software to reset the
PIS field of the Timer Status Register (TSR).
This is done by using
mtspr
to write a word to the TSR having a 1
in
TSR[PIS] and any other bits to
be cleared, and a
0 in all other bits. The data written to the TSR is not direct data, but a mask. A 1
clears a bit; a 0 has no effect.
Using
mtspr
to force the PIT to 0 does not cause a PIT interrupt. However, decrementing that was
ongoing at the instant of the
mtspr
instruction can cause the appearance of an interrupt.
To
eliminate
the
PIT as a source of interrupts, write a 0 to TCR[PIE], the PIT interrupt enable bit.
To
eliminate all PIT activity:
1.
Write a 0 to TCR[PIE]. This prevents PIT activity from causing interrupts.
2. Write a
0 to TCR[ARE]. This disables the PIT auto-reload feature.
3.
Write zeroes to the PIT to halt PIT decrementing. Although this action does not cause a pit PIT
interrupt to become pending, a near-simultaneous decrement to 0 might have done
so.
4. Write a 1 to TSR[PIS] (PIT Interrupt Status bit). This clears TSR[PIS] to 0 (see ''Timer Status
Register (TSR)" on page 11-8). This also clears any pending PIT interrupt. Because the PIT stops
decrementing, no further
PIT events are possible.
If the auto-reload feature is disabled (TCR[ARE] =
0)
when the PIT decrements to
0,
the PIT remains
o until software uses
mtspr
to reload it.
After a reset, TCR[ARE]
= 0, which disables the auto-reload feature.
11-4
PPC405GP User's Manual Preliminary
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