3.11.8 TLB Management Instructions
The TLB management instructions read and write entries of the TLB array
in
the MMU, search the
TLB array for an entry which will translate a given address, and
invalidate all TLB entries. There is
also an instruction for synchronizing TLB updates with other processors, but because the
PPC405GP
is for use
in
uniprocessor environments, this instruction performs no operation.
Table 3-34 lists the TLB management instructions.
In
the table, the syntax "[.]" indicates that the
instruction has a
"record" form that updates CR[CRO], and a "non-record" form.
Table 3-34.
TLB
Management
Instructions
tibia
tlbre
tlbsx[.]
tlbsync
tlbwe
3.11.9 Processor Management Instructions
These instructions move data between the GPRs and SPRs, the CR, and DCRs in the PPC405GP,
and provide traps, system calls, and synchronization controls.
Table 3-35 lists the processor management instructions
in
the PPC405GP.
Table 3-35.
Processor
Management
Instructions
elelo mcrxr
mtcrf
Isync mfcr mtdcr
sync mfdcr mtspr
mfspr sc
tw
twl
3.11.10 Extended Mnemonics
In
addition to mnemonics for instructions supported directly by hardware, the PowerPC Architecture
defines numerous
extended mnemonics.
An extended mnemonic translates directly into the mnemonic; of a hardware instruction, typically with
carefully specified operands. For example, the PowerPC Architecture does not define a "shift right
word immediate" instruction, because the
"rotate left word imm'ediate then AND with mask:'
(rlwinm)
instruction can accomplish the same result:
rlwinm
RA,RS,32-n,n,31
However, because the required operands are not obvious, the
PowerPC Architecture defines an
extended mnemonic:
srwi
RA,RS,n
Extended mnemonics transfer the problem of remembering complex or frequently used operand
combinations to the assembler, and can more clearly reflect a programmer's intentions. Thus,
programs can be more readable.
Refer to the
following chapter and appendixes for lists of the extended mnemonics:
Preliminary
Programming Model 3-53
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