entries that correspond to frequently used storage by electing to never replace them, so that those
entries are never cast out of the TLB.
TLB management is performed by software with some hardware assist, consisting of:
• Storage of the missed EA in the Save/Restore Register 0 (SRRO) for an instruction-side miss,
or
in
the Data Exception Address Register (DEAR) for a data-side miss.
• Instructions for reading, writing, searching, and invalidating the TLB, as described briefly in the
following subsections. See Chapter 24, "Instruction Set:' for detailed instruction descriptions.
6.5.1
TLB Search Instructions (t1bsxltlbsx.)
tlbsx
locates entries in the TLB, to find the TLB entry associated with an interrupt,
or
to locate
candidate entries to cast out.
tlbsx
searches the UTLB array for a matching entry. The EA is the value
to be matched; EA = (RAIO)+(RB).
If
the TLB entry is found, its index is placed
in
RT 26:31' RT can then serve as the source register for a
tlbre
or
tlbwe
instruction to read
or
write the entry, respectively. If no match is found, the contents of
RT are undefined.
tlbsx.
sets the Condition Register (CR) bit
CRO
EO
' The value of
CROEO
depends on whether an entry
is found:
CRO
EO
= 1 if an entry is found;
CROEO
= 0 if no entry is found.
6.5.2 TLB ReadlWrite Instructions (tlbre/tlbwe)
TLB entries can be accessed for reading and writing by
tlbre
and
tlbwe,
respectively. Separate
extended mnemonics are
available for the TLBHI (tag) and TLBLO (data) portions of a TLB entry.
6.5.3 TLB Invalidate Instruction (tibia)
tibia
sets TLB_entry[V] = 0 to invalidate all TLB entries. All other TLB entry fields remain unchanged.
Using
tlbwe
to set TLB_entry[V] = 0 invalidates a specific TLB entry.
6.5.4 TLB Sync Instruction (tlbsync)
tlbsync
guarantees that all TLB operations have completed for all processors
in
a multi-processor
system. PPC405GP provides no multiprocessor support, so this instruction performs no function. The
instruction is
included to facilitate code portability.
6.6 Recording Page References and Changes
When system software manages virtual memory, the software views physical memory as a collection
of pages. Each page is associated with at least one TLB entry.
To
manage memory effectively, system
software often must know whether a
particular page has been referenced
or
modified. Note that this
involves more than knowing whether a particular TLB entry was used to reference or alter memory,
because
multiple TLB entries can translate to the same page.
When system software manages a demand-paged environment, and the software needs to
replace
the contents of a page with other data, previously referenced pages (accessed for any purpose) are
!'Dore
likely to be maintained than pages that were never referenced. If the contents of a page must be
Preliminary Memory Management
6-11
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