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IBM PowerPC 405GP User Manual

IBM PowerPC 405GP
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17.5.3.37 Power Management State Change Request Register (PCICO_PMSCRR)
PCICO_PMSCRR provides a method of informing the local processor of a power management state
change request and prevents the
completion of the write to PCICO_PMCSR until the local processor
indicates it is ready for the state change.
All writes to PCICO_PMCSR are retried until the local
processor sets PCICO_PMSCRR[APW] =
1.
PCICO_PMSCRR is used with the registers
in
the
capability structure for power management. Descriptions of each bit are shown
in
Figure 17-58:
SCR DWE
* *
t
APW REOST
Figure 17-58. Power Management State Change Request Register (PCICO_PMSCRR)
7:5 Reserved
Always read as
0.
4
APW
Accept PMCIO_PCMSR Writes
The local processor sets APW when the
Always 1 if DWE is
0.
local processor is ready to change the
power management state. APW is cleared
when the host configuration writes to the
PCICO_PMCSR register is accepted. The
local processor can write ยฐ to APW.
3
SCR State Change Request
The PCI bridge sets SCR when a host
writes
PCICO_PMCSR to request a power
management state change. This drives an
interrupt to the
local processor informing it
of a state change request. The
local
processor must simultaneously clear SCR
and set APW = 1 when the local processor
is ready to change the state. After
SCR is
cleared, new requests are not detected
until the outstanding
delayed write is
accepted. The
local processor can set
SCR =
1.
Note that any host side write to
any byte
(Ox5C-Ox5F) is considered a
power state change request.
2:1
REOST
Request State
Indicates the new power management
state requested by a
delayed host write to
PCICO_PMCSR. This field is read-only
from the PLB side.
ยฐ
DWE
Delayed Write Enable
When DWE is set to 1 , any configuration
ยฐ Immediate write
write to the PCICO_PMCSR is completed
1 Delayed write
as a
delayed write. All writes to
PCICO_PMCSR are retried until the local
processor sets the "Accept PCICO_PMCSR
Write bit" (bit 4). When
0,
any configuration
write to the
PCICO_PMCSR is completed
immediately.
DWE is a don't care if a host
write to
PCICO_PMCSR requests a state
change from D3hot to
DO.
17-54 PPC405GP User's Manual
Preliminary

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IBM PowerPC 405GP Specifications

General IconGeneral
BrandIBM
ModelPowerPC 405GP
CategoryComputer Hardware
LanguageEnglish

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