8.6.2 Contents
of
Special Purpose Registers after Reset
In
general, the contents of Special Purpose Registers (SPRs) are undefined after a core, chip, or
system reset. Some SPRs retain the contents they had before a reset occurred.
Table 8-2 shows the contents of SPRs that are defined or unchanged after core, chip, and system
resets.
Table 8-2. SPR Contents After Reset
Register Bits/Fields Core Reset Chip Reset System Reset
Comment
DSCRO
EDM
0
0
0
External
debug mode
disabled
RST
00 00
00
No
reset action.
DSCR1
0:31
OxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
Instruction, data compares
disabled
DSSR
MRR
01
10
11
Most recent reset
DCCR
SO:S31
OxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
Data cache disabled
ESR
0:31
OxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
No
exception syndromes
ICCR
SO:S31
oxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
Instruction cache disabled
PVR
0:31
Processor version
SGR
GO:G31
OxFFFFFFFF
OxFFFFFFFF OxFFFFFFFF Storage
is
guarded
SLER
SO:S31
OxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
Storage
is
big endian
SUOR
KO:K31
OxOOOOOOOO
OxOOOOOOOO
OxOOOOOOOO
Storage
is
uncompressed
8.7
OCR
Contents after Reset
DCR reset values are unaffected by core resets and are generally identical for chip and system
resets.
Table 8-3.
DCR
Contents After Reset
Register Bits Reset Value Comment
Chip
Control
CPO_PSR
0:31
At POR,
CPCO_PSR
fields are set
to
the strapping values of
the corresponding pins.
CPCO_PSR
is
rea.d-only.
CPCO_CRO
0:31
OxOOOOO03C
CPCO_CR1
0:31
Ox2BODB800
CPCO_JTAGID
0:31
Refer to PPC405GP Embedded Processor Data Sheet for the
value of this read-only register.
CPCO_PLLMR
0:31
At
POR, CPCO_PLLMR fields are set
to
strapping values
of
the
corresponding pins.
CPCO_PLLMR
is
read-only.
Clock
and Power Management (CPM)
CPCO_ER
0:31
OxFFFF8000
CPCO_ERO:16
return
1,
CPCO_ER
17
:
31
return
O.
8-4
PPC405GP User's Manual
Preliminary
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