standard header and is not a multi-function device; therefore, PCICO_HDTYPE.is read-only and
returns
OxOO
when read.
01
Figure 17-33.
PCI
Header Type Register (PCICO_HDTYPE)
1 PCI Header Type
17.5.3.12 PCI Built-In Self Test (BIST) Control Register (PCICO_BIST)
PCICO_BIST is used for control and status of BIST. PCI bridge does not implement BIST. PCIBIST is
read-only and returns
OxOO
when read.
01
Figure 17-34.
PCI
Built-in Self Test Control Register (PCICO_BIST)
1
7
:
0
1 PCI BIST Control
17.5.3.13 Unused
PCI
Base Address Register Space
PCI base address register space is defined to begin at offset
Ox1
0; however, the first 32 bits
of
this
space are unused by
PCI bridge, and the defined base address registers begin
at
offset Ox14.
17.5.3.14 PCI PTM 1 BAR (PCICO_PTM1 BAR)
PCICO_PTM1 BAR defines a space in PCI memory space mapped to PLB space (system
memory
or
ROM).
Preliminary
PCl,lnterface
17-37
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