Chapter 10. Interrupt Controller Operations
The PPC405GP contains a universal interrupt controller (UIC) that provides all necessary control,
status, and communication between the various internal and external interrupt sources and the
processor core.
10.1
UIC
Overview
The UIC supports 19 internal interrupts and 7 external interrupts. Status reporting (using the UIC
Status Register [UICO_SR]) is provided to ensure that systems software can determine the current
and interrupting state of the system and respond
appropriately. Software can generate interrupts to
simplify software development and for diagnostics.
The interrupts can be programmed, using the
UIC Critical Register (UICO_CR), to generate either a
critical
or
a non-critical interrupt signal to the processor core.
The privileged
mtdcr
and
mfdcr
instructions, which are used by system software, are used to read
and write the
UIC registers.
An
optional critical interrupt vector generator can reduce interrupt handling latency for critical
interrupts. Vector calculation is described
in
detail
in
"UIC Vector Register (UICO_VR)" on page 10-18.
10.2
UIC
Features
• Support for 19 internal and 7 external interrupts
• Support for asychronous level-
or
edge-sensitive interrupt types
• Programmable polarity for all interrupt types
• Programmable critical/non-critical interrupt selection for each interrupt bit
• Prioritized critical interrupt vector generation
• A UIC Status Register (UICO_SR) providing the following information:
- Current state of interrupts
- Current state of
all enabled interrupts (those masked using the UIC Enable Register (UICO_ER))
1
0.3
UIC
Interrupt Assignments
The UIC supports various internal and external interrupt sources as shown
in
Table 10-1.
Table 10-1. UIC
Interrupt
Assignments
Interrupt
Polarity
Sensitivity
Interrupt Source
0
High Level
UARTO
1 High Level
UART1
2 High
Level
IIC
Preliminary
Interrupt Controller
Operations
10-1
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