IBM PowerPC 405GP User Manual

17.2.2 PCI-to-PLB Half-Bridge
As shown in Figure 17-3, the PCI target interface and 64-bit PLB master interface function together as
a
PCI-to-PLB half-bridge to enable PCI master devices to access PLB slave devices. The half-bridge
configuration contains a 63-byte write post buffer and a 96-byte read prefetch buffer.
17.2.3 PCI Arbiter
PLB Master Interface
Read
Prefetch
Buffer
Write
Post
Buffer
PCI Target Interface
Acknowledge
Request
PCI Master
PCI Bridge
Figure 17-3. PCI-to-PLB Half-Bridge Block Diagram
The
internal arbiter can be used with up to six external PCI masters (six Req/Gnt pairs) or can be
disabled. When the internal arbiter is disabled, there is one Req/Gnt pair that must be attached to an
external arbiter. A strapping pin determines whether the internal arbiter is enabled or not. Priority is
round-robin (rotating). Priority switches when a master begins a transfer by asserting Frame. Each
block keeps a priority bit that only switches if its highest priority requestor receives a grant. Assuming
that
all priority bits are initially cleared and all requests are active, an example rotation would be
PPC405GP 3, 1, 5, 0, 4, 2. PCI Specification, Version 2.2 requires that all PCI devices three-state
their pins during reset. The
PPC405GP PCI arbiter supports bus parking during normal operation.
Figure 17-4 shows the
logical arbitration structure.
PPC405GP Bridge PCI Master
PCIReqO
PCIReq1
PCIReq2
PCIReq3
PCIReq4
PCIReq5
------'
Figure 17·4. Arbitration Structure
Preliminary
Arbitration Winner
PCllnterface
17·5

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English