IBM PowerPC 405GP

If software updates a translation/protection mechanism (UTLB, PID, ZPR, or MSR) and must
synchronize these updates with the
ITLB, the software must perform the necessary context
synchronization.
A
typical example is the manipulation of the TLB by an operating system within an interrupt handler
for a TLB miss. Upon entry to the interrupt handler, the ITLB is invalidated and translation is disabled.
If the operating system simply made the TLB updates and returned from the handler (using rfi), no
additional
explicit software action would be required to synchronize the ITLB.
If, instead, the operating system re-enables translation within the handler, and then performs TLB
updates within the handler, those updates
would not be effective in the ITLB until rfi is executed to
return from the handler. For those TLB updates to be reflected in the
ITLB within the handler, an
isyne must be issued after TLB updates finish. Failure to properly synchronize the ITLB can cause
unexpected behavior.
Programming Note: As a rule of thumb, follow software manipulation of an translation
mechanism (if performed
while translation is active) with a context-synchronizing operation
(usually isyne).
6.4 TLB-Related Interrupts
The processor relies on interrupt handling software to implement paged virtual memory, and to
enforce protection of specified memory pages.
When an interrupt occurs, the processor
clears MSR[IR, DR]. Therefore, at the start of all interrupt
handlers, the processor operates
in real mode for instruction accesses and data accesses. Note that
when address translation is disabled for an instruction fetch or load/store, the EA is
equal to the real
address and is passed directly to the memory subsystem (including cache units). Such untranslated
addresses bypass
all memory protection checks that would otherwise be performed by the MMU.
When translation is enabled, MMU accesses can
result in the following interrupts:
• Data storage interrupt
• Instruction storage interrupt
• Data TLB miss interrupt
• Instruction TLB miss interrupt
6.4.1 Data Storage Interrupt
A data storage interrupt is generated when data address translation is active, and the desired access
to the EA is not permitted for one of the
following reasons:
• In the problem state
- iebi, load/store, debz, or
debf with an EA whose zone field is set to no access (ZPR[Zn] = 00).
In this case, debt and debtst no-op, rather than cause an interrupt. Privileged instructions
cannot cause data storage interrupts.
- Stores, or debz, to an EA having TLB_entry[WR]
= a (write access disabled) and ZPR[Zn] -:t:- 11.
(The privileged instructions debi and deeei are treated as "stores", but cause program
interrupts, rather than data storage interrupts.)
Preliminary Memory Management 6-9