IBM PowerPC 405GP

Figures
Figure 1-1. PPC405GP Block Diagram ........................................................................................................... 1-2
Figure 2-1.
Overlapped PLB Transfers ........................................................................................................... 2-4
Figure 2-2.
PLB Arbiter Control Register (PLBO_ACR) .................................................................................. 2-5
Figure 2-3.
PLB Error Address Register (PLBO_BEAR) ................................................................................. 2-6
Figure 2-4.
PLB Error Status Register (PLBO_BESR) .................................................................................... 2-6
Figur'e 2-5. Bridge Error Address Register (POBO_BEAR) ............................................................................. 2-8
Figure 2-6. Bridge Error Status Register
° (POBO_BESRO) ........................................................................... 2-9
Figure 2-7. Bridge Error Status Register 1
(POBO_BESR1) ......................................................................... 2-10
Figure 2-8. OPB Arbiter Control Register (OPBAO_CR) ............................................................................... 2-12
Figure 2-9.
OPB Arbiter Priority Register (OPBAO_PR) ............................................................................... 2-13
Figure 3-1.
PPC405GP Programming Model-Registers ............................................................................... 3-5
Figure 3-2.
General Purpose Registers (RO-R31) .......................................................................................... 3-6
Figure 3-3. Count Register (CTR) ................................................................................................................... 3-8
Figure 3-4. Link Register (LR) ......................................................................................................................... 3-8
Figure 3-5. Fixed
Point Except,ion Register (XER) ........................................................................................ 3-10
Figure 3-6. Special Purpose Register General (SPRGQ-SPRG7) ............................................................... 3-11
Figure 3-7. Processor Version Register (PVR) ............................................................................................. 3-12
Figure 3-8. Condition Register (CR) ............................................................................................................. 3-13
Figure 3-9. Machine
State Register (MSR) ................................................................................................... 3-15
Figure
3-10. PPC405GP Data Types ............................................................................................................ 3-26
Figure 3-11.
Normal Word Load or Store (Big Endian Storage Region) ....................................................... 3-32
Figure 3-12. Byte-Reverse Word Load or
Store (Little Endian Storage Region) .......................................... 3-32
Figure 3-13. Byte-Reverse Word Load or
Store (Big Endian Storage Region) ............................................. 3-33
Figure 3-14.
Normal Word Load or Store (Little Endian Storage Region) .................................................... 3-33
Figure 3-15.
PPC405GP Instruction Pipeline ................................................................................................ 3-34
Figure 4-1.,
Instruction Flow ............................................................................................................................ 4-3
Figure 4-2. Core Configuration Register
° (CCRO) ....................................................................................... 4-11
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR) .................................................................... 4-14
Figure 5-1.
OCM Address Usage .................................................................................................................... 5-2
Figure 5-2.
OCM Instruction-Side Address Range Compare Register (OCMO_ISARC) ................................ 5-5
Figure 5-3.
OCM Instruction-Side Control Register (OCMO_ISCNTL) ............................................................ 5-6
Figure 5-4.
OCM Data-Side Address Range Compare Register (OCMO_DSARC) ........................................ 5-7
Figure 5-5.
OCM Data-Side Control Register (OCMO_DSCNTL) ................................................................... 5-7
Figure 6-1. Effective to
Real Address Translation Flow .................................................................................. 6-2
, Figure 6-2. TLB Entries ............................................................................................................... ~ ................... 6-3
Figure 6-3.
ITLB/DTLB/UTLB Address Resolution ......................................................................................... 6-8
Figure 6-4.
Process ID (PID) ......................................................................................................................... 6-13
Figure 6-5.
Zone Protection Register (ZPR) ................................................................................................. 6-14
Figure 6-6. Generic Storage Attribute
Control Register ................................................................................ 6-18
Figure 7-1.
PPC405GP Clocking .................................................................................................................... 7-1
Figure 7-2. PLL Mode Register (CPCO_PLLMR) .......................................................................................... 7-10
Figure 7-3. Chip Control Register ° (CPCO_CRO) ........................................................................................ 7-12
Preliminary
Figures xxix