1.4.4.2 Debug Modes
The internal, external, real-time-trace, and debug wait modes support a variety of debug tool used
in
embedded systems development. These debug modes are described
in
detail
in
"Debug Modes" on
page 12-6.
1.4.5
Processor
Core Interfaces
The processor core provides a range of
1/0
interfaces.
1.4.5.1 Processor Local Bus
The PLB-compliant interface provides separate 32-bit address and 64-bit data buses for the
instruction and data sides.
1.4.5.2 Device Control Register Bus
The Device Control Register (DCR) bus interface provides access to on-Chip registers for
configuration and status of peripherals such as
SDRAM, DMA and so on.
These registers are accessed using the
mfdcr
and
mtdcr
instructions.
1.4.5.3 Clock and Power Management
This interface supports several methods of clock distribution and power management.
1.4.5.4
JTAG
The JTAG port is enhanced to support the attachment of a debug tool such as the RISCWatch
product from IBM Microelectronics. Through the JTAG test access port, a debug tool can single-step
the processor and interrogate internal processor state to facilitate software debugging. The
enhancements comply with the
IEEE 1149.1 specification for vendor-specific extensions, and are
therefore compatible with standard JTAG hardware for boundary-scan system testing.
1.4.5.5 Interrupts
The processor core provides an interface to the UIC, an on-chip interrupt controller that is logically
outside the processor core. The
UIC combines asynchronous interrupt inputs from on-chip and off-
chip sources and presents them to the processor core using a pair of interrupt signals: critical and
non-critical.
1.4.5.6 On-Chip Memory
The on-chip memory (OCM) interface supports the implementation of instruction- and data-side
memory that can be accessed at performance levels matching the cache arrays.
The
PPC405GP provides 4KB of OCM.
1.5 Processor Core Programming Model
The programming model is described
in
detail
in
Chapter
3,
"Programming Model:'
Preliminary Overview 1-9
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