g.
Enable the channel CE=1.
Once the DMA channel is active, the peripheral initiates a transfer by activating the DMAReqn pin for
the
channel. The PPC405GP then activates the DMAAckn pin to read data from the peripheral. This
continues
until either a terminal count
or
end of transfer condition occurs.
Memory-to-Peripheral Transfer
To
perform a memory-to-peripheral DMA transfer to an EBC-attached DMA peripheral:
1.
Set source address register (DMAO_SAn) to the desired memory location. The address must be
aligned to the programmed transfer width (DMAO_CRn[PWD, otherwise an alignment error will
occur.
2.
Program the count register (DMAO_CTn) for the number of transfers.
3.
Clear the channel's status bits
in
the DMA status register (DMAO_SR).
4.
In the channel control register (DMAO_CRn):
a.
Optionally enable the DMA buffer, BEN=1, and set the desired prefetch count,
PF.
b.
Optionally enable parity generation, PCE=1.
c.
Set the source address increment, SAI=1.
d. Set the transfer mode to peripheral,
TM=ObOO.
e.
Set the peripheral location to external,
PL=O.
f.
Set the transfer direction to memory-to-peripheral
TD=O.
g. Enable the channel, CE=1.
Once the DMA channel is active, the peripheral initiates a transfer
by
activating the DMAReqn pin for
the
channel. The PPC405GP then reads the source memory and subsequently activates the
DMAAckn pin to write data to the
peripheral. This continues until either a terminal count
or
end of
transfer condition occurs.
18.9.2 Memory-to-Memory Transfers
Memory-to-memory transfers can be initiated either by software
or
by an external device. If initiated
via software, the transfer begins as soon as the
channel is configured and enabled. When initiated by
hardware
(also known as a device-paced memory-to-memory transfer), software configures the
channel for a memory-to-memory move and transfers begin when an external device places an active
request on the
channel request line, DMAReqn.
Hardware-Initiated (Device-Paced) Memory-to-Memory Transfers
To
perform a device-paced memory-to-memory DMA transfer:
1.
Set the transfer width (DMAO_CRn[PWD to the width of the device-paced memory.
2.
Set the source (DMAO_SAn) and destination (DMAO_DAn) address registers to the desired
memory
locations. These addresses must be aligned to the programmed transfer width
(DMAO_CRn[PWD, otherwise an
alignment error will occur.
3.
Program the count register (DMAO_CTn) for the number of transfers.
4.
Clear the channel's status bits
in
the DMA status register (DMAO_SR).
5.
In the channel control register (DMAO_CRn):
a.
Optionally enable the DMA buffer, BEN=1, and set the desired prefetch count,
PF.
18-20
PPC405GP User's Manual Preliminary
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