Chapter 17. PCI Interface
17.1
PCI Overview
The peripheral component interconnect (PCI) interface and bridge (referred to as PCI bridge in this
chapter) provides a means for connecting
PCI-compliant devices to the on-chip bus architecture of
the PPC405GP chip. The
PCI bridge complies with PCI Specification, Version 2.2. The PCI bridge is
bidirectional
in
that it allows PPC405GP PLB masters to access PCI targets off-chip. It also allows
PCI
masters to access PLB slave devices such as the SDRAM controller. The
PCI
bridge contains an
arbiter which can
optionally be used for host applications.
The PCI bridge is configurable by an external PCI agent, allowing it to be used
in
target adapter
applications. The PCI bridge contains address mapping register sets to provide address mapping for
both transaction directions. See Figure 17-3
on
page 17-5 for a graphic overview
of
the PCI bridge.
Agents on the PLB are referred to as masters or
slaves. Agents on the PCI are referred to as targets
or
slaves.
17.1.1
PCI
Bridge Features
• PLB bus frequency up to 100 MHz
• PCI bus frequency up to 66 MHz (asynchronous)
or
33 MHz (synchronous)
• Asynchronous clocking between PLB and PCI buses (optional)
•
Supports
1:1,2:1,3:1,
and
4:1
clock ratios from PLB to PCI
•
32-bit PCI Address/Data Bus
• Power Management
• Buffering:
-
PCI target 64-byte write post buffer
-
PCI
target 96-byte read prefetch buffer
- PLB
slave 32-byte write post buffer
- PLB
slave 64-byte read prefetch buffer
• Error tracking/status
• PCI arbitration function (optional)
•
Supports PCI target-side configuration
• Supports processor access to all PCI address spaces:
-
Single-beat PCI I/O reads and writes
-
PCI memory Single-beat and prefetch-burst reads and single-beat writes
-
Single-beat PCI configuration reads and writes (type 0 and type
1)
- PCI interrupt acknowledge
Preliminary PCI Interface
17-1
To Next Page
Loading...
Need help?
General
