2.
Clear MSR[EE] and MSR[CE] to mask interrupts, to ensure that interrupts do not interfere with
the cache
invalidation described in Step
4.
This avoids a potential problem with "dirty" cache
addresses that
would not be fetched from the cache because they have been marked as non-
cachable.
3.
Mark the address region to be programmed as OCM address space as noncachable.
4.
Invalidate the cache array that corresponds to the OCM (instruction-side or data-side) whose
address range compare register is to be modified to ensure that no addresses to be
programmed as
OCM addresses exist
in
the cache. A single
iccci
instruction invalidates the ICU
cache array.
To
invalidate the DCU cache array, use a sequence of
dcbf
instructions (one per
cache
line).
5.
Modify the value
in
OCMO_ISARC
or
OCMO_DSARC.
6.
Set OCMO_ISCNTL[ISEN] = 1 to enable instruction-side OCM accesses, or set
OCMO_DSCNTL[DSEN] = 1 to enable data-side OCM accesses.
• Self-modifying code that accesses OCM to update instructions should not fetch instructions from
the area being modified
until a
sync
instruction executes, followed by an
isync
instruction.
The
sync
instruction ensures that instructions are updated. The
isync
instruction ensures that only
updated instructions are fetched into the pipeline.
Instructions
in
OCM can be updated while instructions from non-OCM addresses execute. A
sync-
isync
pair should still be used whenever such self-modifying code is updated.
• The CPU can become less efficient when instructions and data
in
OCM are accessed at the same
time, because the SRAM has
only one access port and instruction fetches have the lowest priority.
For
example, instructions fetched from OCM that contain several sequential data-side loads
accessing OCM can result
in
bubbles
in
the instruction pipeline. The sequential data-side loads
dominate OCM accesses, resulting
in
the inability to fetch instructions from OCM.
• If aliased
addresses are used, the aliased 4KB address spaces should be aligned on 16KB
boundaries to
eliminate potential store data bypass problems, as described
in
"Store Data Bypass
Behavior and Memory Coherency:'
5.3 Store Data Bypass Behavior and Memory Coherency
The OCM subsystem provides only one mechanism, data-side store operations, for writing both
instructions and data into the
OCM array. However, two independent mechanisms request read
access of
OCM contents; one for instruction-side fetches and the other for data-side loads.
The following description applies only to applications that alias the OCM address space and perform
a mix of data-side
loads and stores. It does not apply to applications that use data-side stores only to
initialize
OCM with instructions.
If a data-side OCM store is followed
in
the next cycle by a data-side load, the load actually accesses
the
OCM array before the store. This is due to the nature of the processor pipeline, the cycle
availability of the store data, and the fact that data-side loads have a higher priority than data-side
stores.
In this scenario, store data is queued
in
a register while the load accesses the array. Further, if
the store is immediately
followed by a sequence of consecutive loads, it remains
in
the queue until the
last of the consecutive loads has accessed the OCM array. The queued store data is written into the
OCM array
in
the first cycle that does not have a data-side load operation accessing the array.
Preliminary On-Chip Memory
5-3
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