17.6
Error
Handling
The PCI bridge detects and reports several types of errors, which are reported
to
the PLB
or
the PCI.
Status information is saved
in
the configuration registers to enable error type determination.
All errors are associated with either a cycle on the PLB
or
a cycle on the PCI bus.
Each error that can be detected is associated with a mask.
If the mask is set, detection of that error
condition is
disabled. There are also masks for the PCISErr, PCIPErr, and PLB bus error signals that
prevent reporting of any error by these
signals. The masks do not prevent error detection.
The error types are as
follows:
•
PLB unsupported transfer type
• PCI master abort generated (while PCI master)
•
PCI
target abort received (while PCI master)
• PCI target data bus parity error detection
• PCI master data bus parity error detection
• PCI target address parity error detection
• PLB bus error detection
The
following sections describe in detail how these errors are generated, what actions are taken for
each, and how to reset a given error.
17.6.1 PLB Unsupported Transfer Type
This error occurs when the bridge PLB slave encounters an unsupported PLB transfer type.
Table 17-11 outlines transfers not supported by the bridge PLB slave.
Table 17-11.
PLB
Unsupported Transfer Types
PLB Transaction PCI
Address
Space
4- and 8-word line read/write
Nonmemory
16-word
line read/write
Any
Burst Nonmemory
Upon detection of this error, the bridge sets PCICO_ERRSTS[PUR] =
1.
17.6.2
PCI
Master
Abort
This error is generated by the bridge PCI master when no target responds with PCIDevSel within the
required time-out window and error detection is
enabled. The bridge PLB slave may assert a PLB bus
error
signal on the PLB
in
response to this error, as explained below.
Two
masks are associated with a PCI master abort. PCICO_ERREN[MAEE] masks error reporting. If
the error is detected, a PLB bus error signal is asserted if PCICO_ERREN[MAEE] = 1. For reads, the
bridge PLB
slave still completes the transfer on the PLB, but drives 1 s on the read data bus and the
appropriate PLB bus error
signal for each data beat. For posted writes, a PLB bus error is asserted for
Preliminary
PCI
Interface
17-55
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