16 EE External Interrupt Enable
Controls the non-critical external interrupt
o Asynchronous interrupts (external to the
input,
PIT,
and FIT interrupts.
processor core) are
disabled.
1 Asynchronous interrupts are enabled.
17 PR Problem State
o Supervisor state (all instructions
allowed).
1 Problem state (some instructions not
allowed).
18 Reserved
...
19 ME Machine Check Enable
o Machine check interrupts are disabled.
1 Machine check interrupts are enabled.
20 Reserved
21
OWE
Debug Wait Enable
o Debug wait mode is disabled.
1 Debug wait mode is enabled.
22 DE Debug Interrupts Enable
o Debug interrupts are disabled.
1 Debug interrupts are enabled.
23:25 Reserved
26
IR Instruction Relocate
o Instruction address translation is
disabled.
1 Instruction address translation is
enabled.
27
DR Data Relocate
o Data address translation is disabled.
1 Data address translation is enabled.
28:31 Reserved
3.3.6 Device Control Registers
Device Control Registers (DCRs), on-chip registers that exist architecturally outside the processor
core, are not part of the
IBM PowerPC Embedded Environment. The Embedded Environment simply
defines the existence of a
DCR address space
and
the instructions that access the DCRs, but does
not define any DCRs. The instructions that access the DCRs are mtdcr (move to device control
register) and mfdcr (move from device control register).
DCRs are used to control the operations of on-chip buses, peripherals, and some processor behavior.
3-16 PPC405GP User's Manual Preliminary
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