To
complete a line fill, the DCU must access the tag and data arrays. The tag array is read to
determine the tag addresses, the LRU
line, and whether the LRU line is dirty. A dirty cache line is one
that was accessed by a store instruction after the
line was established, and can be inconsistent with
external memory. If the line being replaced is dirty, the address and the cache line must be saved so
that
external memory can be updated. During the cache line fill, the LRU bit is set to identify the line
opposite the line just filled as LRU.
When a
line fill completes and replaces a dirty line, a line flush begins. A flush copies updated data
in
the data cache array to main storage. Cache flushes are always sequential, starting at the first word
of the cache
line and proceeding sequentially to the end of the line.
Cache lines are always completely flushed or filled, even if the program does not request the rest of
the bytes
in
the line,
or
if a bus error occurs after a bus interface unit accepts the request for the line
fill. If
a bus error occurs during a line fill, the line is filled and the data is marked valid. However, the
line can contain invalid data, and a machine check exception occurs.
4.2.2
DCU
Write Strategies
DCU operations can use write-back
or
write-through strategies to maintain coherency with external
cachable
memory.
The write-back strategy updates
only the data cache, not external memory, during store operations.
Only modi.tied data lines are flushed to external memory, and then only when necessary to free up
locations for incoming lines,
or
when lines are explicitly flushed using
dcbf
or
dcbst
instructions. The
write-back strategy minimizes the amount of
external bus activity and avoids unnecessary contention
for the
external bus between the ICU and the DCU.
The write-back strategy is contrasted with the write-through strategy,
in
which stores are written
simultaneously to the cache and to external memory. A write-through strategy can simplify
maintaining coherency between cache and memory.
When data address translation.is
enabled (MSR[DR] = 1), the W storage attribute
in
the TLB entry for
the memory page
controls the write strategy for the page. If TLB_entry[W] = 0, write-back is selected;
otherwise, write-through is selected. The write strategy is controlled separately for each page.
''Translation Lookaside Buffer (TLB)" on page 6-2 describes the TLB.
When data address
translation is disabled (MSR[DR] = 0), the Data Cache Write-through Register
(DCWR) sets the storage attribute. Each bit
in
the DCWR (DCWR[WO:W31]) controls the write
strategy of a 128MB storage region (see
"Real-mode Storage,Attribute Control" on page 6-17). If
DCWR[Wn] =
0,
write-back is enabled for the specified region; otherwise, write-through is enabled.
Programming
Note:
The PowerPC Architecture does not support memory models
in
which
write-through is
enabled and caching is inhibited.
4.2.3
DCU
Load and Store Strategies
The DCU can control whether a load receives one word
or
one line of data from main memory.
For
cachable memory, the load without allocate (LWOA) field of the
CCRO
controls the type of load
resulting
from a load miss. If CCRO[LWOA] =
0,
a load miss causes a line fill. If CCRO[LWOA] =
1,
load misses do not result
in
a line fill, but
in
a word load from external memory. For infrequent reads of
non-contiguous memory,
set~ing
CCRO[LWOA] = 1 may provide a small performance improvement.
Preliminary Cache Operations 4-7
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