mapped PCI address space, SDRAM memory, and memory and memory-mapped devices on the
peripheral bus. During a peripheral mode transfer the peripheral requests a DMA transfer by asserting
a DMA request
line. For
UARTO,
this signal is internal to the PPC405GP, while external peripherals
use one of the DMAReqn lines. When the requesting channel has the highest priority of any active
channel, the requesting device receives a DMA acknowledge. In the case of external peripherals, the
appropriate DMAAckn
line is driven to the active state, with the timing specified in the
DMA
Control
Register for the channel (DMAO_CRn).
There are two types of peripheral mode transfers: peripheral-to-memory and memory-to-peripheral. A
peripheral-to-memory transfer reads data from a DMA device,
while a memory-to-peripheral transfer
writes data.
In
both cases, the peripheral interface never bursts and data is transferred at the width of
the
peripheral. If the DMA buffer is disabled for the active channel (DMAO_CRn[BEN]=O), each
peripheral transfer causes a corresponding memory operation.
When buffering is
enabled during a peripheral-to-memory transfer, data is collected until the 32-byte
buffer is
full, the peripheral deasserts DMAReqn, a higher priority DMA request becomes pending,
or
the channel completes. The buffer contents are then written to the target memory as efficiently as
possible. If the initial programming of the channel's destination address register (DMAO_DAn) is 32-
byte
aligned, the buffer is emptied in one burst operation to the target memory.
Memory-to-peripheral transfers differ since the amount of data that
will be requested by the peripheral
is unknown. If the DMA buffer is disabled (DMAO_CRn[BEN]=O) a discrete source memory read
occurs for each
element
in
the DMA transfer. Since this is inefficient, the buffer should only be
disabled for low data rate transfers
or
when the source memory is FIFO-like, and reads are therefore
destructive. When the 32-byte buffer is
enabled the controller uses the setting
in
DMAO_CRn[PF] to
prefetch
1,
2,
or 4 64-bit doublewords from the source memory. The DMA controller provides data
from the buffer
until the peripheral deasserts its request, the channel is interrupted by one of higher
priority,
or
the transfer completes. Whenever any of these conditions occurs any unused data
in
the
DMA buffer is discarded.
18.2.2 Memory-to-Memory Transfers
The DMA controller can perform either device-paced (hardware-initiated)
or
software-initiated
memory-to-memory transfers. Device-paced memory transfers function
identically to peripheral mode
transfers, except that a chip
select (PerCSn) serves as the DMA acknowledge instead of a DMAReqn
output. As with
peripheral mode transfers, bursts never occur on the device-paced side of the
transaction.
Software-initiated memory-to-memory transfers between memories with fixed timings provide the
best
overall performance. During a software-initiated transfer the DMA controller knows the exact
amount of data to be transferred. As a
result, when the 32-byte DMA buffer is enabled
(DMAO_CRn[BEN]=1) the controller uses bursts as much as possible.
To
ensure the highest
bandwidth, source and destination addresses
should be aligned on 32-byte boundaries.
There are three cases that
limit the ability to burst during software-initiated memory-to-memory
transfers. Bursting is not
possible from the source memory when the source address increment is
zero
(DMAO_CRn[SAI]=O). Similarly, the DMA controller does not burst to the destination when the
destination address increment is zero
(DMAO_CRn[DAI]=O). Finally, the DMA controller cannot burst
to
or
from any address that maps to a device-paced (EBCO_BnAP[RE]=1) EBC chip select (PerCSn).
Preliminary
Direct Memory Access Controller
18-3
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