1.5.2.4 Condition Register
The processor core contains a 32-bit Condition Register (CR). These bits are grouped into eight 4-bit
fields, CR[CRO]-CR[CR7]. Instructions are provided to perform logical operations on
CR
fields and
bits within
fields and to test CR bits within fields. The CR fields, which are set by compare
instructions, can be used to
control branches. CR[CRO] can be set implicitly by arithmetic instructions.
1.5.2.5
Device
Control Registers
DCRs, which are architecturally outside of the processor core, are accessed using the mtdcr and
mfdcr instructions. DCRs are used to
control, configure, and hold status for various functional units
that are not part of the processor core.
The mtdcr and mfdcr instructions are
privileged, for all DCRs. Therefore, all accesses to DCRs are
privileged. See "Privileged Mode Operation" on page 3-41.
1.5.3 Memory-Mapped I/O Registers
The memory-mapped I/O (MMIO) registers are accessed using load and store instructions. MMIO
registers, which are outside processor core and which are not architected, are useq to control,
configure, and hold status for various functional units that are not part of the processor core.
1.5.4 Addressing Modes
The processor core supports the following addressing modes, which enable efficient retrieval and
storage of data
in
memory:
• Base plus displacement addressing
• Indexed addressing
• Base plus displacement addressing and indexed addressing, with update
In
the base plus displacement addressing mode, an effective address (EA) is formed by adding a
displacement to a base address contained in a GPR (or to an implied base of 0). The displacement is
an immediate
field
in
an instruction.
In
the indexed addressing mode, the EA is formed by adding an index contained in a GPR to a base
address contained
in
a GPR (or to an implied base of 0).
The base plus displacement and the indexed addressing modes also have a "with update" mode. In
"with
update" mode, the effective address calculated for the current operation is saved
in
the base
GPR, and can be used as the base
in
the next operation. The "with update" mode relieves the
processor from
repeatedly loading a GPR with an address for each piece of data, regardless of the
proximity of the data
in
memory.
Preliminary
Overview
1-11
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