IBM PowerPC 405GP User Manual

10.15 Instruction Storage Interrupt
The instruction storage interrupt is generated when instruction translation is active and execution is
attempted for an instruction whose fetch access to the effective address is not permitted for any
of the
following reasons:
• In Problem State:
- Instruction fetch from an effective address with
(ZPR field) = 00.
- Instruction fetch from an effective address with the EX bit clear and (ZPR field) ¢ 11.
- Instruction fetch from an effective address contained within a Guarded region (G=1).
• In Supervisor State:
- Instruction fetch from an effective address with the EX bit clear and
(ZPR field) other than 11 or
10.
- Instruction fetch from an effective address contained within a Guarded region (G=1).
SRRO will save the address of the instruction causing the instruction storage interrupt.
ESR is set to indicate the following conditions:
• If ESR[DIZ] = 1, the excepting condition was a zone fault: the attempted execution of an instruction
address fetched
in user-mode with (ZPR field) = 00.
• If ESR[DIZ] = 0, then the excepting condition was either EX = 0 or G = 1.
The interrupt is precise with respect to the attempted execution of the instruction. Program flow
vectors to
EVPR[0:15] " Ox0400.
The following registers are modified to the specified values:
Table 10-11. Register Settings during Instruction Storage Interrupts
SRRO
Set to the EA of the instruction for which execute access was not permitted
SRR1
Set to the value of the MSR at the time of the interrupt
MSR WE, EE, PR, OWE, IR, OR f- 0
GE, ME, OE f- unchanged
PC EVPR[0:15] II Ox0400
ESR
OIZ
f- 11f access failure due to a zone protection fault (ZPR[Zn] = 00 in user
mode)
Note:
If ESR[OIZ] is not set, the interrupt occurred because TBL_entry[EX]
was clear
in an otherwise accessible zone, or because of an instruction
fetch from a storage region marked as guarded.
See "Exception Syndrome
Register
(ESR)" on page 10-31 for details of ESR operation.
Mel f- unchanged
All other bits are cleared.
10.16 External Interrupt
External interrupts (external to the processor core) are triggered by active levels for non-critical
interrupts
in the UIC. All external interrupting events are presented to the processor as a single
external interrupt. External interrupts are enabled or disabled by MSR[EE].
10-38 PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English