IBM PowerPC 405GP User Manual

About This Book
This user's manual provides the architectural overview, programming model, and detailed information
about the registers, the instruction set, and operations of the
IBM PowerPC 405GP (PPC405GP)
32-bit
RISC embedded processor.
The PPC405GP
RISC embedded processor features:
• PowerPC Architecture ™
• Single-cycle execution for most instructions
• Instruction cache unit and data cache unit
• Support for Little Endian operation
• Interrupt interface for one critical and one non-critical interrupt signal
•
JTAG interface
• Extensive development tool support
Who Should Use This Book
This book is for system hardware and software developers, and for application developers who need
to understand the PPC405GP. The audience
should understand embedded processor design,
embedded system design, operating systems,
RISC processing, and design for testability.
How to Use This Book
This book describes the PPC405GP device architecture, programming model, external interfaces,
internal registers, and instruction set. This book contains the following chapters, arranged in parts:
Part
I Introducing the PPC405GP Embedded Processor
Chapter 1 Overview
Chapter 2
On-Chip Buses
Part
II The PPC405GP RISC Processor
Chapter 3 Programming
Model
Chapter 4 Cache Operations
Chapter 5
On-Chip Memory
Chapter
6 Memory Management
Part
III PPC405GP System Operations
Chapter
7 Clocking
Chapter 8 Reset and Initialization
Chapter 9 Pin Strapping and Sharing
Chapter
10 Interrupt Controller Operations
Chapter
11 Timer Facilities
Chapter 12 Debugging
Chapter 13
Clock and Power Management
Chapter 14 Decompression
Controller Operation
Preliminary About This Book xlvii

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English