IBM PowerPC 405GP

28 EIR3E ExternallRO 3 Enable
o An external IRO 3 interrupt is disabled.
1 An externallRO 3 interrupt is enabled.
29
EIR4E External IRO 4 Enable
o An externallRO 4 interrupt is disabled.
1 An externallRO 4 interrupt is enabled.
30 EIR5E
ExternallRO
5 Enable
o An external IRO 5 interrupt is disabled.
1 An external IRO 5 interrupt is enabled.
31 EIR6E External IRO 6 Enable
o An externallRO 6 interrupt is disabled.
1 An externallRO 6 interrupt is enabled.
10.5.3 UIC Critical Register (UICO_CR)
The fields of the UICO_CR, which correspond to the fields of the UICO_SR and UICO_ER, determine
whether an interrupt captured in the corresponding
fields of the UICO_SR generates a non-critical or
critical interrupt, if the interrupts are enabled in the corresponding fields of the UICO_ER. The
processor
handles critical interrupts when MSR[EE] = 1 and non-critical interrupts when MSR[CE]=1.
If a UICO_CR field is set to 0, an enabled interrupt (captured in the corresponding field of the
UICO_SR and enabled in the corresponding field of the UICO_ER) generates a non-critical interrupt
signal to the processor core. If a UICO_CR field is a 1, a critical interrupt signal is generated.
UOIC IICIC PCIIC D11C D31C MSIC MREIC MRDIC EPSIC PPMIC
EIR1C EIR3C EIR5C
1
U11T EMIC DOIC D21C EWIC MTEIC MTDIC ENIC ECIC
EIROC EIR2C EIR4C EIR6C
Figure 10-3. UIC Critical Register (UICO_CR)
0
UOIC UARTO Interrupt Class
o UARTO interrupt is non-critical.
1 UARTO interrupt is critical.
1 U11C UART1 Interrupt Class
o UART1 interrupt is non-critical.
1 UART1 interrupt is critical.
2 IICIC
IIC Interrupt Class
o IIC interrupt is non-critical.
1 IIC interrupt is critical.
3 EMIC External Master Interrupt Class
o External master interrupt is non-critical.
1 External master interrupt is critical.
4 PCIIC PCI Interrupt Class
o PCI interrupt is non-critical.
1 PCI interrupt is critical.
10-8
PPC405GP User's Manual
Preliminary