The following register values provide the address map shown
in
Figure 17-59:
Table 17-12.
Address
Map
Register
Values
Register Name Value
Comments
PCILO_PMMOLA
Ox20000000
PCILO_PMMOMA
OxF8000001
128MB; enabled;
read
prefetching not allowed.
PCILO_PMMOPCILA
Ox20000000
PCILO_PMMOPCIHA
OxOOOOOOOO
PCILO_PMM1
LA
Ox28000000
PCILO_PMM1
MA
OxFCOOOOO3
64MB; enabled; prefetching allowed.
PCILO_PMM1
PCILA Ox30000000
PCILO_PMM1
PCIHA
OxOOOOOOOO
PCILO_PMM2LA
OxOOOOOOOO
PCILO_PMM2MA
OxOOOOOOOO
Not enabled.
PCILO_PMM2PCILA
OxOOOOOOOO
PCILO_PMM2PCIHA
OxOOOOOOOO
PCILO_PTM1
MSr
OxFOOOOOO1
256MB; enabled.
PCILO_PTM1
LA
OxOOOOOOOO
PCILO_PTM2MS
OxOOOOOOOO
Not enabled.
PCILO_PTM2LA
OxOOOOOOOO
PCICO_PTM1
BAR
OxOOOOOO08
PCI
memory space; address decode starts at
PCI
address
OxOOOO
0000.
PCICO_PTM2BAR
OxOOOOOOOO
17.9.2 Other Configuration Register Initialization
Additional register initialization is required, as follows:
•
Error handling is initially disabled (error detection is masked). If error handling is to be enabled,
PCICO_ERREN
must be initialized appropriately.
• PCICO_BRDGOPT1 contains options for controlling the PLB. Its default values can be used.
• PCICO_BRDGOPT2 contains options for controlling the PCI bus. Its default values assume that the
PCI is run synchronously to the PLB, and that the PCI bridge is the primary host bridge. If the PCI
bridge is used otherwise, the values must be changed accordingly.
17.9.3 Target Bridge Initialization
The PCI bridge can also respond as a configuration target; however, the PCI bridge only responds as
a configuration target when the
PCIIDSel pin is attached, rather than pulled inactive. Note that if the
size and
local address of these ranges are not strapped to desired values at reset, the local CPU
must specify them by setting the PTM Memory Size and Local Address registers before initializing
PCICO_PTM1
BAR and PCICO_PTM2BAR.
Preliminary
PCI
Interface
17-63
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