IBM PowerPC 405GP User Manual

5.4 Registers
The OCM controller uses the D~vice Control Registers (DCRs) listed in Table 5-2.
Table 5-2. OCM DCRs
Register Mnemonic DCR Number Access Page
OCM Instruction-Side Address Range Compare Register OCMO_ISARC Ox018 RIW
5-5
OCM Instruction-Side Control Register OCMO_ISCNTL Ox019 RIW 5-6
OCM Data-Side Address Range Compare Register OCMO_DSARC Ox01A RIW 5-6
OCM Data-Side Control Register OCMO_DSCNTL Ox01B RIW 5-7
5.4.1 OCM Instruction-Side Address Range Compare Register (OCMO_ISARC)
OCMO_ISARC defines the address range of the OCM controller when it is presented with instruction
fetch requests.
OCMO_ISARC[ISAR] is compared to the high-order 6 bits of the requested instruction
address, providing a 64MB address space. The address space can be shared with,
or distinct from,
the data-side
OCM address space.
The
OCM controller returns requested instructions if instruction-side OCM access is enabled
(OCMO_ISCNTL[ISEN]
= 1) and OCMO_ISARC[ISAR] matches the high-order 6 bits of the requested
instruction address.
OCMO_ISARC must be initialized before OCMO_ISCNTL[ISEN] is set to 1 to enable instruction-side
OCM accesses. See "OCM Initialization" on page 8-13 for details
ISAR
10
*
516 311
Figure 5-2. OCM Instruction-Side Address Range Compare Register (DCMO_ISARC)
Instruction-side OCM address range
Reserved
Preliminary
On-Chip Memory 5-5

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English