IBM PowerPC 405GP

10.4 Interrupt Programmability
The on-chip interrupts (interrupts 0-18) and the externallRQs (interrupts 25-31) are programmable.
However, the polarity and sensitivity of the on-chip interrupts must be programmed as shown in
Table 10-1, using the UIC Polarity Register (UICO_PR) and UIC Trigger Register (UICO_ TR),
respective
Iy.
10.5 ule Registers
The UIC includes the Device Control Registers (DCRs) listed in Table 10-2.
The registers are accessed using the mfdcr and mtdcr instructions.
Table
10-2. UIC DCRs
Mnemonic Register
Address Access
UICO_SR UIC Status Register
OxOCO Read/Clear
UICO_ER
UIC Enable Register
OxOC2 RIW
UICO_CR UIC Critical Register OxOC3 RIW
UICO_PR
UIC Polarity Register
OxOC4 RIW
UICO_TR
UIC Trigger Register
OxOC5 RIW
UICO_MSR UIC Masked Status Register
OxOC6
Read-only
UICO_VR
UIC Vector Register
OxOC7
Write-only
UICO_VCR UIC Vector Configuration Register
OxOC8
Read-only
10.5.1 UIC Status Register (UICO_SR)
Page
10-3
10-6
10-8
10-10
10-13
10-16
10-19
10-18
To report interrupt status, the UICO_SR fields capture and hold internal and external interrupts until
the fields are intentionally reset. To reset a field, write 1 to the field.
The values of other UIC registers do not affect UICO~SR fields.
UIOS IIGIS PGIIS 011S 031S MSIS MREIS MROIS EPSIS PPMIS
EIR1S EIR3S EIR5S
UI1 SEMIS OOIS 021S EWIS MTEIS MTOIS EN IS EGIS
EIROS EIR2S EIR4S EIR6S
Figure 10-1. UIC Status Register (UICO_SR)
0 UOIS UARTO Interrupt Status
o A UARTO interrupt has not occurred.
1 A
UARTO interrupt occurred.
1
U11S UART1 Interrupt Status
o A UART1 interrupt has not occurred.
1 A
UART1 interrupt occurred.
Preliminary
Interrupt
Controller Operations
10-3