IBM PowerPC 405GP User Manual

10.5.6 UIC Masked Status Register (UICO_MSR)
This read-only register contains the result of masking the UICO_SR with the UICO_ER. Reading this
register, instead of the
actual UICO_SR, eliminates the need for software to read and apply the enable
mask to the contents of the UICO_SR to determine which enabled interrupt fields are active.
If an interrupt is configured as level-sensitive, and a clear is attempted on the UICO_SR, the UICO_SR
field
is not cleared if the incoming interrupt signal is at the asserted polarity. The interrupt signal must
be reset before the
UICO_SR can be successfully cleared.
UIOS IICIS PCIIS 011S 031S MSIS MREIS MROIS EPSIS PPMIS EIR1S EIR3S EIR5S
UI1S EMIS OOIS 021S EWIS MTEISMTOIS ENIS ECIS EIROS EIR2S EIR4S EIR6S
Figure 10-6. UIC Masked Status Register (UICO_MSR)
0 UOIS UARTO Masked Interrupt Status
o A UARTO interrupt has not occurred.
1 A
UARTO interrupt occurred.
1
U11S
UART1 Masked Interrupt Status
o A UART1 interrupt has not occurred.
1 A
UART1 interrupt occurred.
2
IICIS
IIC Masked Interrupt Status
o An IIC interrupt has not occurred.
1 An
IIC interrupt occurred.
3 EM IS
External Master Masked Interrupt Status
o An external master interrupt has not
occurred.
1 An external master interrupt occurred.
4
PCIIS PCI Masked Interrupt Status
o A PCI interrupt has not occurred.
1 A
PCI interrupt occurred.
5
DOIS
DMA Channel 0 Masked Interrupt Status
o A DMA channel 0 interrupt has not
occurred.
1 A DMA channel
0 interrupt occurred.
6 D11S
DMA Channel 1 Masked Interrupt Status
o A DMA channel 1 interrupt has not
occurred.
1 A DMA channel 1 interrupt occurred.
7 D21S
DMA Channel 2 Masked Interrupt Status
o A DMA channel 2 interrupt has not
occurred.
1 A DMA channel 2 interrupt occurred.
10-16
PPC405GP User's Manual
Preliminary

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English