IBM PowerPC 405GP User Manual

16.7 Error Reporting
The EBC monitors four kinds of errors when performing read and write transfers. Of these four, bank
protect and external bus errors are always checked, while timeout and read parity error checking must
be enabled via DCR-mapped configuration registers.
• Protect Error - Requested read or write operation violates the bank usage programmed in
EBCO_BnCR[BU]. For example, write attempt to read-only bank.
In all cases, no external bus
activity occurs.
• External Bus Error - The PerErr input was sampled active during the data transfer cycle of a read
or write operation. The associated data is read or written as usual. .
• Timeout Error - This error is possible during memory operations when both PerReady sampling is
enabled, EBCO_BnAP[RE]=1, and device paced timeouts are enabled,
EBCO_CFG[PTD]=O.
Whenever the peripheral address bus changes the EBC begins counting PerClk cycles. If the count
reaches the value represented by EBCO_CFG[RTC] a timeout error occurs. Note that timeout
errors are not possible during the peripheral portion of DMA transfers.
• Parity Error - Indicates that the parity calculated for the read data did not match the parity read.
Parity generation and checking is enabled for memory operations by setting EBCO_BnAP[PEN]=1
and for DMA peripheral transfers by programming DMAO_CRn[PCE]=1.
When the EBC slave detects one of the above errors it reports the error condition to the PLB
master that initiated the transfer. The EBC also logs the type of error into
EBCO_BESRO or
EBCO_BESR1 and the address of the error in EBCO_BEAR.
16.7.1 Error Locking
The PCI Bridge and Media Access Layer (MAL) controllers may qualify their PLB transactions to the
EBC such that the information describing any errors that occur during these transfers becomes
iocked. When an error is locked, subsequent errors are not permitted to overwrite the information
detailing the first error.
When a master requests error locking an error locks not only the EBCO_BESRn field for the master,
but also the EBCO_BEAR. These remain locked until software clears them. For each PLB master that
supports error locking the EBC has a EBCO_BESRn field containing two bits associated with error
locking.
One is the field lock bit and the other is the address lock bit. When an error is detected with
locking enabled the field lock bit is set to a value of one. Setting the field lock bit prevents subsequent
errors for this master from being logged and overwriting the contents of the field.
In addition, the
address lock bit is set if no other master has previously locked the EBCO_BEAR.
Once the
EBCO_BEAR
is locked, no future errors from this or any master can update the EBCO_BEAR until
software clears the lock bits. When software processes an error it should clear the error status and
both lock bits at the same time.
16.7.2 Peripheral Bus Error Address Register (EBCO_BEAR)
The Peripheral Bus Error Address Register (EBCO_BEAR) is a 32-bit register containing the address
of the access where a data bus error occurred.
If the master that initiated the transfer requested error
locking, and the EBCO_BEAR is not already locked, the contents of EBCO_BEAR are locked until the
lock bit
in one of the Peripheral Bus Error Status Registers (EBCO_BESRO or EBCO_BESR1) is
cleared. The contents of the EBCO_BEAR are accessed indirectly through the EBCO_CFGADDR and
EBCO_CFGDATA registers using the
mfdcr and mtdcr instructions.
External Bus Controller 16-29

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English