IBM PowerPC 405GP User Manual

• BWT (Burst Wait, bits 6:8) - Specifies the number of wait states to be taken by accesses beyond
the first during a burst transfer (field BME = 1).
On burst accesses except for the last, the number of
cycles from address valid to the next valid address on each burst access is
(1 + BWT), where
° ~ BWT ~ 7. On the last burst access, the numberof cycles from address valid to the deassertion
of
PerCSn is (1 + BWT), where ° ~ BWT ~ 7.
• CSN (Chip Select On Timing, bits 12: 13) - Specifies the chip select turn on delay relative to the
address.
PerCSn may turn on coincident with the address or be delayed by 1, 2, or 3 PerClk cycles.
• OEN (Output Enable On Timing, bits 14:15) - Specifies when the output enable signal, PerOE, is
asserted for read operations relative to the chip select signal.
If 0, PerDE is asserted coincident
with the chip select.
If 1, 2 or 3, PerOE is delayed by 1, 2, or 3 PerClk cycles.
• WBN (Write Byte Enable On Timing, bits 16:17) - Specifies when the write byte enables,
PerWBEO:3, are asserted relative to the chip select signal. If 0, then PerWBEO:3 turns on
coincident with the chip select.
If 1, 2, or 3, then PerWBEO:3 is delayed 1, 2, or 3 PerClk cycles
from the chip select.
• WBF (Write Byte Enable Off Timing, bits 18: 19) - Specifies when the write byte enables are
deasserted, relative to the deassertion of the chip select signal.
If WBF=O, PerWBEO:3 goes high
coincident with the chip select signal.
If WBF is 1, 2, or 3, then PerWBEO:3 turns off 1, 2, or 3
PerClk cycles before the turn-off of the chip select signal.
Programming Note: It is an error to set WBF > BWT. Moreover, for device-paced transfers
(EBCO~BnAP[RE]=1) WBF must be set to zero.
• TH (Transfer Hold, bits 20:22) - Specifies the number of PerClk cycles (0 through 7) that the
peripheral bus is held idle after the deassertion of
PerCSn. During these cycles, the address bus
and data bus are active and
PerR/W is valid. During the hold time, chip select, output enable, and
write byte enables are inactive.
If Ready Mode is used (RE=1) along with Sample on Ready
(SOR=1) TH must be set to at least
1.
• RE (Ready Enable, bit 23) - Controls the use of the PerReady input signal. If RE=O, the PerReady
input is ignored and no additional wait states are inserted into bus transactions. If RE=1, the
PerReady input is examined after the wait period expires; additional wait states are inserted if the
PerReady input is 0. The maximum number of wait states in each transaction is determined by the
settings
in the Device-Paced Timeout Disable (PTD) and Ready Timeout Counter (RTC) fields in
EBCO_CFG. If EBCO_CFG[PTD]=O, the ready timeout function is disabled and the PPC405GP
waits indefinitely until PerReady=1. If EBCO_CFG[PTD]=1 , the PPC405GP waits the number of
cycle indicated by EBCO_CFG[RTC] cycles for
PerReady to become active. If PerReady does not
become active
in the allotted time, the address of the error is logged in EBCO_BEAR and the type
of error is captured in either
EBCO_BESRO or EBCO_BESR1.
• SOR (Sample Ready, bit 24) - Controls the location of the data transfer cycle with respect to the
PerReady input. If SOR=1 the data transfer occurs on the same PerClk edge that PerReady is
sampled active, whereas if
SOR=O the data transfer occurs one cycle later.
• BEM (Byte Enable Mode, bit 25) - Controls whether PerWBEO:3 is active during writes or for both
reads and writes.
• PEN (Parity Enable Mode, bit 26) - Enables parity generation and checking.
16-28 PPC405GP User's Manual

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English