Table 18-7. Upon receiving the data from the scatter/gather descriptor table, the channel's terminal
count status bit (DMAO_SR[TCn]) is automatically cleared.
Table 18-7. DMA Registers Loaded
from
Scatter/Gather
Descriptor
Table
Descriptor
Table
Entry
Register
Loaded
Channel Control Word
DMAO_CRn
Source Address
DMAO_SAn
Destination Address
DMAO_DAn
Count
DMAO_CTn
Next Descriptor Address
DMAO_SGn
After loading the channel's registers from the descriptor table, the transfer functions as a normal non-
scatter/gather operation.
If the channel control word loaded from the descriptor table enables interrupts for the channel
(DMAO_CRn[CIE]=1),
the TCI, ETI, and ERI bits further qualify the generation of interrupts. See
"DMA Interrupts"
on page 18-15 for more information on scatter/gather interrupts.
If
the LK (link) bit was not set the scatter/gather process stops when the current transfer completes.
Otherwise, the DMA controller reads the descriptor table at address DMAO_SGn and the process
repeats.
18.9 Programming the DMA Controller
Before the DMA controller can transfer data it must be configured, both globally and on a per-channel
basis. Global settings include the DMA Polarity Register (DMAO_POL) and DMA Sleep Mode
Register
(DMAO_SLP). For most applications, these registers should be configured when the DMA
controller is first initialized.
To
prevent spurious activity resulting from changing the active level for
DMAReqn, DMAAckn, or EOTn[TCn], a
channel's configuration
in
the Polarity Register should not be
altered when the channel is enabled (DMAO_CRn[CE]=1).
Each
channel has a Control (DMAO_CRn), Source Address (DMAO_SAn), Destination Address
(DMAO_DAn), Count (DMAO_CTn), and Scatter/Gather Descriptor Address
(DMAO_SGn) register.
The type of DMA transfer determines which of these registers must be programmed and what causes
the
channel to start.
In
all cases, the terminal count (CSn), end of transfer (TSn) and error status (Rln)
bits
in
the DMA Status Register (DMAO_SR) must be cleared
or
the channel will not start.
The programming information that
follows assumes that the DMA controller is operating
in
non-
scatter/gather mode.
To
use scatter/gather transfers the channel configuration data must be written
into a set of descriptor
tables
in
system memory. See "Scatter/Gather Transfers" on page 18-16 for
additional details.
18.9.1 Peripheral Mode Transfers
DMA peripherals are either devices attached to the EBC interface via the DMAReqn and DMAAckn
lines,
or
the internal serial port (UARTO). During a peripheral mode transfer an external peripheral
asserts DMAReqn to request a DMA transfer. For metastability protection DMAReqn is double
latched
in
the DMA upon assertion, and sampled with a single latch
on
the deassertion.
Preliminary
Direct Memory Access Controller
18-17
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