4.1.2 Instruction Cachability Control
When instruction address translation is enabled (MSR[IR] = 1), instruction cachability is controlled by
the
I storage attribute
in
the translation lookaside buffer (TLB) entry for the memory page. If
TLB_entry[l] =
1,
caching is inhibited; otherwise caching is enabled. Cachability is controlled
separately for each page, which can range
in
size from 1 KB to 16MB. "Translation Lookaside Buffer
(TLB)" on page 6-2 describes the TLB.
When instruction address translation is disabled
(MSR[IR] = 0), instruction cachability is controlled by
the
Instruction Cache Cachability Register (ICCR). Each field
in
the ICCR (ICCR[SO:S31]) controls
the cachability of a 128MB region (see
"Real-mode Storage Attribute Control" on page 6-17). If
ICCR[Sn]
=
1,
caching is enabled for the specified region; otherwise, caching is inhibited.
The performance of the
PPC405GP is significantly lower while fetching instructions from cache-
inhibited regions.
Following system reset, address translation is disabled and all ICCR bits are reset to 0 so that no
memory regions are cachable. Before regions can be designated as cachable, the
ICU cache array
must
be
invalidated. The
iccci
instruction must execute before the cache is enabled. Address
translation can then be enabled, if required, and the TLB or the
ICCR can then be configured for the
required cachability.
4.1.3 Instruction Cache Synonyms
The following information applies only if instruction address translation is enabled (MSR[IR] = 1) and
1 KB or 4KB page sizes are used.
See Chapter
6,
"Memory Management," for information about
address translation and page sizes.
An instruction cache synonym occurs when the instruction cache array contains multiple cache lines
from the same real address.
Such synonyms result from combinations of:
• Cache array size
• Cache associativity
• Page size
• The use of effective addresses (EAs) to index the cache array
For example, the instruction cache array has a
"way size" of 8KB (16KB array/2 ways). Thus,
11
bits
(EA
19
:
29
)
are needed to select a word (instruction)
in
each
way.
For the minimum page size of 1
KB,
the low order 8 bits (EA
22
:
29
)
address a word
in
a page. The high order address bits (EA
o
:
21
) are
translated to form a real address (RA), which the
ICU uses to perform the cache tag match. Cache
synonyms could occur because the index bits (EA
19
:
29
)
overlap the translated RA bits. For 1 KB
pages, overlap
in
EA
19
:
21
and RA
19
:
21
could result
in
as many as 8 synomyms.
In
other words, data
from the same RA could occur as as manyas 8
lIocations in the cache array. Similarly, for 4KB pages,
EA
o
:
19
are translated. Differences in EA
19
and RA
19
could result
in
as many as 2 synonyms. For the
next largest page size (16KB), only EA
0:17 are translated. Because there is no overlap with index bits
EA
19
:
21
, synonyms do not occur.
4-4 PPC405GP User's Manual
Preliminary
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