If a DMA channel is setup for scatter/gather transfers (DMA_SGC[SSGn]=1) the count register is
automatically loaded from memory. For additional details see "Scatter/Gather Transfers" on
page 18-16.
The
value
in
the DMA count register is interpreted as the number of
transfers
of the width specified
in
DMAO_CRn[PW],
not
the total number of bytes. The maximum number of transfers is 64K, and each
transfer can be either
1,
2,
4,
or
8 bytes as programmed
in
DMAO_CR[PW]. The maximum count of
64K transfers is programmed by writing zero to DMAO_CTn.
NTR
+
1
0
151
16
Figure
18-8.
DMA
Count
Registers
(DMAO_CTO-DMAO_CT3)
Reserved
Number of transfers remaining
18.3.8 DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-
DMAO_SG3)
When a DMA channel is setup for scatter/gather transfers (DMA_SGC[SSGn]=1), the Scatter/Gather
Descriptor Address Register (DMAO_SGn) contains the memory address of the next scatter/gather
descriptor
table. Prior to starting a scatter/gather transfer, software must write the address of the
channel's descriptor table to DMAO_SGn. Once the scatter/gather transfer starts, DMAO_SGn is
automatically updated from the descriptor table. For additional details see "Scatter/Gather Transfers"
on page 18-16.
1
0
18-12
31\
DMA
Scatter/Gather
Descriptor
Address
Registers
(DMAO_SGO-DMAO_SG3)
Address of next scatter/gather descriptor
table.
PPC405GP User's Manual Preliminary
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