Figure 9-1. Chip Pin Strapping Register (CPCO_PSR) ..................................................................................
9-1
Figure 10-1. UIC Status Register (UICO_SR) ............................................................................................... 10-3
Figure 10-2. UIC Enable Register (UICO_ER) .............................................................................................. 10-6
Figure 10-3. UIC Critical Register (UICO_CR) .............................................................................................. 10-8
Figure 10-4. UIC Polarity Register (UICO_PR) ................... : ....................................................................... 10-11
Figure 10-5.
UIC Trigger Register (UICO_TR) ............................................................................................ 10-13
Figure 10-6.
UIC Masked Status Register (UICO_MSR) ............................................................................ 10-16
Figure 10-7.
UIC Vector Configuration Register (UICO_VCR) .................................................................... 10-19
Figure 10-8.
UIC Vector Register (UICO_ VR) ............................................................................................. 10-20
Figure 10-9. Machine State Register (MSR) .............................................................................................. 10-28
Figure
10-10. Save/Restore Register 0
(SRRO)
......................................................................................... 10-29
Figure 10-11. Save/Restore Register 1
(SRR1) ......................................................................................... 10-30
Figure 10-12. Save/Restore Register 2 (SRR2) ......................................................................................... 10-30
Figure 10-13. Save/Restore Register 3 (SRR3) ......................................................................................... 10-31
Figure 10-14. Exception Vector Prefix Register (EVPR) ............................................................................ 10-31
Figure 10-15. Exception Syndrome Register
(ESR) ................................................................................... 10-32
Figure 10-16. Data Exception Address Register (DEAR) ........................................................................... 10-34
Figure 11-1.
Relationship of Timer Facilities to the Time Base ....................................................................
11-1
Figure 11-2. Time Base Lower (TBL) ........................................................................................................... 11-2
Figure 11-3. Time Base Upper (TBU) ........................................................................................................... 11-3
Figure 11-4.
Programmable Interval Timer (PIT) ........................................................................................... 11-5
Figure 11-5. Watchdog Timer
State Machine .............................................................................................. 11-7
Figure 11-6. Timer
Status Register (TSR) .................................................................................................... 11-8
Figure 11-7. Timer
Control Register (TCR) .................................................................................................. 11-9
Figure 12-1. JTAG Connector
Physical Layout (Top View) .......................................................................... 12-2
Figure 12-2. JTAG
ID
Register (CPCO_JTAGID) ......................................................................................... 12-4
Figure 12-3.
RISCTrace Header (Top View) ................................................................................................ 12-5
Figure 12-4. Debug
Control Register 0 (DBCRO) ......................................................................................... 12-9
Figure 12-5. Debug
Control Register 1 (DBCR1) ....................................................................................... 12-11
Figure 12-6. Debug
Status Register (DBSR) .............................................................................................. 12-13
Figure 12-7.
Instruction Address Compare Registers (IAC1-IAC4) ........................................................... 12-14
Figure 12-8. Data Address Compare Registers (DAC1-DAC2) ................................................................. 12-15
Figure 12-9. Data
Value Compare Registers (DVC1-DVC2) ..................................................................... 12-15
Figure 12-10.
Inclusive lAC Range Address Compares ............................................................................. 12-18
Figure 12-11. Exclusive
lAC Range Address Compares ............................................................................ 12-18
Figure 12-12.
Inclusive DAC Range Address Compares ........................................................................... 12-20
Figure 12-13. Exclusive DAC Range Address Compares .......................................................................... 12-20
Figure 13-1. CPM Registers (CPCO_ER, CPCO_FR,
CPCO_SR) ................................................................ 13-2
Figure 14-1. Decompression
Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3) ........................ 14-4
Figure 14-2. Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1) ....... 14-5
Figure 14-3. Decompression
Controller Configuration Register (DCPO_CFG) ............................................ 14-6
Figure 14-4. Decompression
Controller
ID
Register (DCPO_ID) .................................................................. 14-6
Figure 14-5. Decompression
Controller Version Register (DCPO_VER) ...................................................... 14-7
Figure 14-6. Decompression
Controller PLB Error Address Register (DCPO_PLBBEAR) ........................... 14-7
Figure 14-7. Decompression
Controller Bus Error Address Register (DCPO_MEMBEAR) ........................... 14-7
Figure 14-8. Decompression
Controller Error Status Register 0 (DCPO_ESR) ............................................ 14-8
xxx
PPC405GP User's Manual Preliminary
To Next Page
Loading...
