IBM PowerPC 405GP

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Table 8-3. OCR Contents After Reset (continued)

CPCO_FR

0:31

OxOOOOOOOO

CPCO_SR 0:31

OxOOOOOOOO

Decompression Controller

DCPO_ADDRO

0:31

OxOOOOOOOO

DCPO_ADDR1

0:31

OxOOOOOOOO

DCPO_MEMBEAR 0:31

OxOOOOOOOO

DCPO_CFG

0:31

OxOOOOOO01

DCPO_ESR

0:31

OxOOOOOOOO

DCPO_ID

0:31

OxOOO0504D

DCPO_ITORO

0:31

OxOOOOOOOO

DCPO_ITOR1

0:31

OxOOOOOOOO

DCPO_ITOR2

0:31

OxOOOOOOOO

DCPO_ITOR3

0:31

OxOOOOOOOO

DCPO_PLBBEAR 0:31

OxOOOOOOOO

DCPO_RAMO-

1KB

Undefined

DCPO_RAM3FF

DCPO_VER

0:31

OxOOOO0200

Direct Memory Access (DMA)

DMAO_CRO

0:31

OxOOOOOOOO

DMAO_CR1

0:31

OxOOOOOOOO

DMAO_CR2

0:31

OxOOOOOOOO

DMAO_CR3

0:31

OxOOOOOOOO

DMAO_CTO

0:31

OxOOOOOOOO

DMAO_CT1

0:31

OxOOOOOOOO

DMAO_CT2

0:31

OxOOOOOOOO

DMAO_CT3

0:31

OxOOOOOOOO

DMAO_DAO

0:31

OxOOOOOOOO

DMAO_DA1

0:31

OxOOOOOOOO

DMAO_DA2

0:31

OxOOOOOOOO

DMAO_DA3

0:31

OxOOOOOOOO

DMAO_POL

0:31

OxOOOOOOOO

DMAO_SAO

0:31

OxOOOOOOOO

DMAO_SA1

0:31

OxOOOOOOOO

DMAO_SA2

0:31

OxOOOOOOOO

Preliminary

Reset

and

Initialization

8-5

Main Page

Table of Contents6
Figures30
About this Book48
Who Should Use this Book48
Conventions49
Part I. Introducing the PPC405GP Embedded Processor52
Chapter 1. Overview54
PPC405GP Features55
Bus and Peripheral Features55
Figure 1-1. PPC405GP Block Diagram55
Powerpc Processor Core Features56
Powerpc Architecture57
The PPC405GP as a Powerpc Implementation58
RISC Processor Core Organization58
Instruction and Data Cache Controllers58
Instruction Cache Unit59
Data Cache Unit59
Memory Management Unit59
Timer Facilities61
Debug61
Development Tool Support61
Debug Modes62
Processor Core Interfaces62
Processor Local Bus62
Device Control Register Bus62
Clock and Power Management62
Jtag62
Interrupts62
On-Chip Memory62
Processor Core Programming Model62
Data Types63
Processor Core Register Set Summary63
General Purpose Registers63
Special Purpose Registers63
Machine State Register63
Condition Register64
Device Control Registers64
Chapter 2. On-Chip Buses66
Processor Local Bus66
PLB Features67
PLB Masters and Slaves67
PLB Master Assignments67
Table 2-1. PPC405GP PLB Agents as Masters and Slaves67
PLB Transfer Protocol68
Table 2-2. Registers Controlling PLB Master Priority Assignments68
Overlapped PLB Transfers69
Figure 2-1. Overlapped PLB Transfers69
PLB Arbiter Registers70
PLB Arbiter Control Register (PLBO_ACR)70
PLB Error Address Register (PLBO_BEAR)70
Table 5-170
PLB Error Status Register (PLBO_BESR)71
PLB to OPB Bridge Registers73
Bridge Error Address Register (POBO_BEAR)73
Bridge Error Status Registers (POBO_BESRO-POBO_BESR1)73
Table 2-4. PLB Arbiter Registers73
On-Chip Peripheral Bus76
OPB Features76
OPB Master Assignments77
OPB Arbiter Registers77
OPB Arbiter Control Register (OPBAO_CR)77
Table 2-6. PLB Arbiter Registers77
OPB Arbiter Priority Register (OPBAO_PR)78
Part II. the PPC405GP Rise Processor80
Chapter 3. Programming Model82
User and Privileged Programming Models82
Memory Organization and Addressing82
Physical Address Map83
Table 3-1. PPC405GP Address Space83
Storage Attributes84
Registers84
Figure 3-1. PPC405GP Programming Model-Registers86
General Purpose Registers (RO-R31)87
Special Purpose Registers87
Figure 3-2. General Purpose Registers (RO-R31)87
Count Register (CTR)88
Link Register (LR)89
Fixed Point Exception Register (XER)89
Figure 3-3. Count Register (CTR)89
Figure 3-4. Link Register (LR)89
Figure 3-5. Fixed Point Exception Register (XER)91
Table 3-3. XER[CA] Updating Instructions91
Special Purpose Register General (SPRGO-SPRG7)92
Table 3-4. XER[SO,OV] Updating Instructions92
Processor Version Register (PVR)93
Condition Register (CR)93
Figure 3-7. Processor Version Register (PVR)93
CR Fields after Compare Instructions94
Figure 3-8. Condition Register (CR)94
The CRO Field95
The Time Base96
Machine State Register (MSR)96
Figure 3-9. Machine State Register (MSR)96
Table 3-5. Time Base Registers96
Device Control Registers97
Directly Accessed Dcrs98
Figure 7-3. Chip Control Register98
Table 3-6. Directly Accessed Dcrs98
Indirectly Accessed Dcrs100
Indirect Access of SDRAM Controller Dcrs100
Table 3-7. SDRAM Controller DCR Usage100
Table 3-8. Offsets for SDRAM Controller Registers100
Indirect Access of External Bus Controller Dcrs101
Table 3-9. External Bus Controller DCR Usage101
Table 3-10. Offsets for External Bus Controller Registers101
Indirect Access of Decompression Controller Dcrs102
Table 3-11. Decompression Controller DCR Usage102
Table 3-12. Offsets for Decompression Controller Registers102
Memory-Mapped Input/Output Registers103
Directly Accessed MMIO Registers103
Table 3-13. Directly Accessed MMIO Registers103
Figure 19-15. Mode Register105
Indirectly Accessed MMIO Registers106
Table 3-15. PCI Configuration Registers106
Data Types and Alignment107
Figure 3-10. PPC405GP Data Types107
Alignment for Storage Reference and Cache Control Instructions108
Alignment and Endian Operation108
Summary of Instructions Causing Alignment Exceptions109
Byte Ordering109
Table 3-16. Alignment Exception Summary109
Structure Mapping Examples110
Big Endian Mapping110
Little Endian Mapping111
Support for Little Endian Byte Ordering111
Endian (E) Storage Attribute111
Fetching Instructions from Little Endian Storage Regions112
Accessing Data in Little Endian Storage Regions112
Powerpc Byte-Reverse Instructions113
Figure 3-11. Normal Word Load or Store (Big Endian Storage Region)113
Figure 3-12. Byte-Reverse Word Load or Store (Little Endian Storage Region)113
Instruction Processing114
Figure 3-13. Byte-Reverse Word Load or Store (Big Endian Storage Region)114
Figure 3-14. Normal Word Load or Store (Little Endian Storage Region)114
Branch Processing115
Unconditional Branch Target Addressing Options115
Conditional Branch Target Addressing Options116
Conditional Branch Condition Register Testing116
BO Field on Conditional Branches116
Table 3-17. Bits of the BO Field116
Branch Prediction117
Table 3-18. Conditional Branch BO Field117
Speculative Accesses118
Speculative Accesses in the PPC405GP118
Prefetch Distance down an Unresolved Branch Path119
Prefetch of Branches to the CTR and Branches to the LR119
Preventing Inappropriate Speculative Accesses119
Fetching Past an Interrupt-Causing or Interrupt-Returning Instruction120
Fetching Past Tw or Twi Instructions120
Fetching Past an Unconditional Branch121
Suggested Locations of Memory-Mapped Hardware121
Table 3-19. Example Memory Mapping121
Privileged Mode Operation122
MSR Bits and Exception Handling122
Privileged Instructions123
Privileged Sprs123
Privileged Dcrs124
Synchronization124
Context Synchronization125
Executio!,,! Synchronization127
Storage Synchronization127
Instruction Set128
Table 3-21. PPC405GP Instruction Set Summary128
Instructions Specific to IBM Powerpc Embedded Processors129
Storage Reference Instructions129
Table 3-22. Implementation-Specific Instructions129
Table 3-23. Storage Reference Instructions129
Arithmetic Instructions130
Table 3-24. Arithmetic Instructions130
Logical Instructions131
Compare Instructions131
Table 3-25. Multiply-Accumulate and Multiply Halfword Instructions131
Table 3-26. Logical Instructions131
Table 3-27. Compare Instructions131
Branch Instructions132
CR Logical Instructions132
Rotate Instructions132
Table 3-28. Branch Instructions132
Table 3-29. CR Logical Instructions132
Table 3-30. Rotate Instructions132
Shift Instructions133
Cache Management Instructions133
Interrupt Control Instructions133
Table 3-31. Shift Instructions133
Table 3-32. Cache Management Instructions133
Table 3-33. Interrupt Control Instructions133
TLB Management Instructions134
Processor Management Instructions134
Extended Mnemonics134
Table 3-34. TLB Management Instructions134
Table 3-35. Processor Management Instructions134
Chapter 4. Cache Operations136
ICU Organization136
Table 4-1. Instruction Cache Organization137
Figure 4-1. Instruction Flow138
Instruction Cachability Control139
Instruction Cache Synonyms139
ICU Coherency140
DCU Organization140
DCU Operations141
Table 4-2. Data Cache Organization141
DCU Write Strategies142
DCU Load and Store Strategies142
Data Cachability Control143
DCU Coherency144
Cache Instructions144
ICU Instructions144
DCU Instructions145
Cache Control and Debugging Features146
Figure 4-2. Core Configuration Register146
CCRO Programming Guidelines148
Figure 4-3. Instruction Cache Debug Data Register (ICDBDR)149
DCU Debugging150
DCU Performance151
Pipeline Stalls151
Cache Operation Priorities152
Table 4-3. Priority Changes with Different Data Cache Operations152
Simultaneous Cache Operations153
Sequential Cache Operations153
Chapter 5. On-Chip Memory154
OCM Programming Guidelines155
Store Data Bypass Behavior and Memory Coherency156
Registers158
Table 5-2. OCM Dcrs158
OCM Instruction-Side Control Register (OCMO_ISCNTL)159
OCM Data-Side Address Range Compare Register (OCMO_DSARC)159
Chapter 6. Memory Management162
MMU Overview162
Address Translation162
Translation Lookaside Buffer (TLB)163
Unified TLB163
Figure 6-1. Effective to Real Address Translation Flow163
TLB Fields164
Page Identification Fields164
Translation Field165
Table 6·1. TLB Fields Related to Page Size165
Access Control Fields166
Storage Attribute Fields166
Shadow Instruction TLB167
ITLB Accesses167
Shadow Data TLB168
DTLB Accesses168
Shadow TLB Consistency169
Figure 6-3. ITLB/DTLB/UTLB Address Resolution169
TLB-Related Interrupts170
Data Storage Interrupt170
Instruction Storage Interrupt170
Data TLB Miss Interrupt170
Instruction TLB Miss Interrupt170
TLB Management171
TLB Search Instructions (Tlbsxltlbsx.)172
TLB Invalidate Instruction (Tibia)172
TLB Sync Instruction (Tlbsync)172
Recording Page References and Changes172
Access Protection173
Access Protection Mechanisms in the TLB173
General Access Protection173
Execute Permissions174
Write Permissions174
Zone Protection174
Figure 6-5. Zone Protection Register (ZPR)175
Access Protection for Cache Control Instructions176
Table 6-2. Protection Applied to Cache Control Instructions176
Access Protection for String Instructions177
Real-Mode Storage Attribute Control178
Storage Attribute Control Registers179
Data Cache Write-Through Register (DCWR)179
Figure 6-6. Generic Storage Attribute Control Register179
Data Cache Cachability Register (DCCR)180
Instruction Cache Cachability Register (ICCR)180
Storage Guarded Register (SGR)180
Storage User-Defined 0 Register (SUOR)180
Part III. PPC405GP System Operations182
Chapter 7. Clocking184
PLL Overview184
Figure 7-1. PPC405GP Clocking184
Input Reference Clock (Sysclk)185
External Clock Strapping Setup186
Table 7-1. Clock Strapping Values186
Sample Clock Ratios187
Table 7-2. PLL Tuning Settings187
Table 7-3. Possible Clocking Ratios for Reference Clock of 33.3Mhz188
Table 7-4. Possible Clocking Ratios for Reference Clock of 25Mhz189
PCI Clocking190
PCI Clocks191
PCI Adapter Applications191
Table 7-6. Example Synchronous PCI Clock Frequencies in Asynchronous Mode191
Serial Port Clocking192
Clocking Registers192
Table 7-7. Clocking Control Registers192
PLL Mode Register (CPCO_PLLMR)193
Chip Control Register 0 (CPCO_CRO)195
Reset and Initialization198
Reset Signals198
Reset Types198
Core Reset198
Chip Reset198
System Reset199
PCI Power Management Initiated Resets199
Processor Initiated Resets199
Processor State after Reset199
Processor Register Contents after Reset200
Machine State Register Contents after Reset200
Table 8-1. MSR Contents after Reset200
Contents of Special Purpose Registers after Reset201
OCR Contents after Reset201
Table 8-2. SPR Contents after Reset201
Table 8-3. DCR Contents after Reset201
MMIO Register Contents after Reset205
Table 8-4. MMIO Register Contents after Reset205
PPC405GP Chip Initialization209
OCM Initialization210
Initializing Instruction-Side OCM210
Initializing Data-Side OCM210
UIC Initialization211
UART Initialization211
PPC405GP Initial Processor Sequencing211
Initialization Requirements212
Initialization Code Example213
Chapter 9. Pin Strapping and Sharing216
Pin Strapping216
Pin Sharing218
Table 9-1. Multiplexed Pins218
Chapter 10. Interrupt Controller Operations220
UIC Overview220
UIC Features220
UIC Interrupt Assignments220
Table 10-1. UIC Interrupt Assignments220
Interrupt Programmability222
UIC Status Register (UICO_SR)222
Table 10-2. UIC Dcrs222
UIC Enable Register (UICO_ER)225
UIC Critical Register (UICO_CR)227
UIC Polarity Register (UICO_PR)229
UIC Trigger Register (UICO_TR)232
UIC Masked Status Register (UICO_MSR)235
UIC Vector Configuration Register (UICO_VCR)237
UIC Vector Register (UICO_VR)238
Using the Value in UICO_VR as a Vector Address or Entry Table Lookup239
Vector Generation Scenarios239
Interrupt Handling in the Processor Core241
Architectural Definitions and Behavior241
Behavior of the PPC405GP Implementation242
Interrupt Handling Priorities243
Table 10-3. Interrupt Handling Priorities244
Critical and Noncritical Interrupts245
General Interrupt Handling Registers246
Table 10-4. Interrupt Vector Offsets246
Machine State Register (MSR)247
Figure 10-9. Machine State Register (MSR)247
Save/Restore Registers 0 and 1 (SRRO-SRR1)248
Figure 10-10. Save/Restore Register 0 (SRRO)248
Save/Restore Registers 2 and 3 (SRR2-SRR3)249
Figure 10-11. Save/Restore Register 1 (SRR1)249
Figure 10-12. Save/Restore Register 2 (SRR2)249
Exception Vector Prefix Register (EVPR)250
Exception Syndrome Register (ESR)250
Figure 10-13. Save/Restore Register 3 (SRR3)250
Figure 10-14. Exception Vector Prefix Register (EVPR)250
Figure 10-15. Exception Syndrome Register (ESR)251
Table 10-5. ESR Alteration by Various Interrupts252
Table 10-6. ESR Alteration by Various Interrupts252
Data Exception Address Register (DEAR)253
Critical Input Interrupts253
Figure 10-16. Data Exception Address Register (DEAR)253
Machine Check Interrupts254
Instruction Machine Check Handling254
Table 10-7. Register Settings During Critical Input Interrupts254
Data Machine Check Handling255
Data Storage Interrupt255
Table 10-8. Register Settings During Machine Check-Instruction Interrupts255
Table 10-9. Register Settings During Machine Check-Data Interrupts255
Table 10-10. Register Settings During Data Storage Interrupts256
Instruction Storage Interrupt257
External Interrupt257
Table 10-11. Register Settings During Instruction Storage Interrupts257
External Interrupt Handling258
Alignment Interrupt258
Table 10-12. Register Settings During External Interrupts258
Table 10-13. Alignment Interrupt Summary258
Program Interrupt259
Table 10-14. Register Settings During Alignment Interrupts259
Table 10-15. ESR Usage for Program Interrupts259
System Call Interrupt260
Programmable Interval Timer (PIT) Interrupt260
Table 10-16. Register Settings During Program Interrupts260
Table 10-17. Register Settings During System Call Interrupts260
Fixed Interval Timer (FIT) Interrupt261
Table 10-18. Register Settings During Programmable Interval Timer Interrupts261
Table 10-19. Register Settings During Fixed Interval Timer Interrupts261
Watchdog Timer Interrupt262
Data TLB Miss Interrupt262
Table 10-20. Register Settings During Watchdog Timer Interrupts262
Table 10-21. Register Settings During Data TLB Miss Interrupts262
Instruction TLB Miss Interrupt263
Debug Interrupt263
Table 10-22. Register Settings During Instruction TLB Miss Interrupts263
Table 10-23. SRR2 During Debug Interrupts264
Table 10-24. Register Settings During Debug Interrupts264
Chapter 11. Timer Facilities266
Figure 11-1. Relationship of Timer Facilities to the Time Base266
Time Base267
Figure 11-2. Time Base Lower (TBL)267
Reading the Time Base268
Writing the Time Base268
Figure 11-3. Time Base Upper (TBU)268
Table 11-1. Time Base Access268
Programmable Interval Timer (PIT)269
Fixed Interval Timer (FIT)270
Figure 11-4. Programmable Interval Timer (PIT)270
Table 11-2. FIT Controls270
Watchdog Timer271
Table 11-3. Watchdog Timer Controls271
Figure 11-5. Watchdog Timer State Machine272
Timer Status Register (TSR)273
Figure 11-6. Timer Status Register (TSR)273
Timer Control Register (TCR)274
Figure 11-7. Timer Control Register (TCR)274
Chapter 12. Debugging276
Development Tool Support276
Debug Interfaces276
IEEE 1149.1 Test Access Port (JTAG Debug Port)276
JTAG Connector277
JTAG Instructions278
JTAG Boundary Scan278
Table 12-2. JTAG Instructions278
JTAG Implementation279
Trace Port280
Figure 12-3. Risctrace Header (Top View)280
Table 12-3. Risctrace Header Pin Description280
Debug Modes281
Internal Debug Mode281
External Debug Mode281
Debug Wait Mode282
Real-Time Trace Debug Mode282
Processor Control283
Processor Status283
Debug Registers283
Debug Control Registers284
Debug Control Register284
Figure 12-4. Debug Control Register 0 (DBCRO)284
Debug Control Register1 (DBCR1)286
Figure 12-5. Debug Control Register 1 (DBCR1)286
Debug Status Register (DBSR)287
Instruction Address Compare Registers (IAC1-IAC4)289
Data Address Compare Registers (DAC1-DAC2)289
Figure 12-7. Instruction Address Compare Registers (IAC1-IAC4)289
Data Value Compare Registers (DVC1-DVC2)290
Figure 12-8. Data Address Compare Registers (DAC1-DAC2)290
Figure 12-9. Data Value Compare Registers (DVC1-DVC2)290
Debug Events291
Branch Taken Debug Event292
Exception Taken Debug Event292
Trap Taken Debug Event292
Unconditional Debug Event292
Lac Debug Event292
Lac Exact Address Compare292
Lac Range Address Compare292
Figure 12-10. Inclusive Lac Range Address Compares293
Figure 12-11. Exclusive Lac Range Address Compares293
DAC Debug Event294
DAC Exact Address Compare294
DAC Range Address Compare294
Data Address Compare (DAC) Applied to Cache Instructions295
Figure 12-12. Inclusive DAC Range Address Compares295
Figure 12-13. Exclusive DAC Range Address Compares295
Data Value Compare Debug Event296
Table 12-7. Comparisons Based on Dbcr1[Dvnm]298
Chapter 13. Clock and Power Management300
CPM Registers300
Table 13-1. CPM Registers300
Chapter 14. Decompression Controller Operation304
Code Compression304
Code Decompression305
Instruction Fetches to Compressed305
Instruction Fetches to Uncompressed306
Performance306
Decompression Controller Registers306
Index Table Origin Registers (DCPO_ITORO-DCPO_ITOR3)307
Table 14-1. Dcrs Used to Access the Decompression Controller Registers307
Table 14-2. Offsets for Decompression Controller Registers307
Decompression Address Decode Definition Registers (DCPO_ADDRO-DCPO_ADDR1)308
Decompression Configuration Register (DCPO_CFG)308
Decompression Controller ID Register (DCPO_ID)309
Decompression Controller Error Status Register (DCPO_ESR)310
Part IV. PPC405GP External Interfaces314
Chapter 15. SDRAM Controller316
Interface Signals316
Figure 15-1. SDRAM Controller Signals316
Table 15-1. SDRAM Signal Usage and State During/Following Reset317
Table 15-5. SDRAM318
Memory Controller Status (SDRAMO_STATUS)320
Memory Bank 0-3 Configuration (SDRAMO_BOCR-SDRAMO_B3CR)321
Page Management322
Logical Address to Memory Address Mapping323
Table 15-6. Logical Address Bit on BA 1:0 and Memaddr12:0 Versus Addressing Mode323
SDRAM Timing Register (SDRAMO_ TR)324
Selected Timing Diagrams325
Table 15-7. SDRAM Memory Timing Parameters325
Figure 15-6. Activate, Four Word Read, Precharge, Activate326
Figure 15-7. Activate, Four Word Write, Precharge, Activate326
Figure 15-8. Precharge All, Activate327
Figure 15-9. CAS before RAS Refresh327
Auto (CAS before RAS) Refresh328
Refresh Timer Register (SDRAMO_RTR)328
Error Checking and Correction (ECC)329
ECC Configuration Register (SDRAMO_ECCCFG)329
Table 15-8. Additional Latency When Using ECC329
Correctable ECC Errors330
Uncorrectable ECC Errors330
Error Locking331
ECC Error Status Register (SDRAMO_ECCESR)331
Bus Error Address Register (SDRAMO_BEAR)332
Bus Error Syndrome Register (SDRAMO_BESRO)332
Bus Error Syndrome Register 1 (SDRAMO_BESR1)333
Self-Refresh334
Power Management335
Sleep Mode Entry335
Power Management Idle Timer (SDRAMO_PMIT)335
Sleep Mode Exit336
Chapter 16. External Bus Controller338
Interface Signals338
Figure 16-1. External Bus Controller Signals339
Table 16-1. EBC Signal Usage and State During/Following a Chip or System Reset339
Interfacing to Byte, Halfword and Word Devices340
Multiplexed Ii0S341
Driver Enables341
Non-Burst Peripheral Bus Transactions342
Table 16-2. Effect of Driver Enable Programming on EBC Signal States342
Single Read Transfer343
Figure 16-3. Single Read Transfer343
Single Write Transfer344
Figure 16-4. Single Write Transfer344
Burst Transactions345
Burst Read Transfer346
Figure 16-5. Burst Read Transfer346
Burst Write Transfer347
Figure 16-6. Burst Write Transfer347
Device-Paced Transfers348
Device-Paced Single Read Transfer349
Figure 16-7. Device-Paced Single Read Transfer349
Device-Paced Single Write Transfer350
Figure 16-8. Device-Paced Single Write Transfer350
Device-Paced Burst Read Transfer351
Figure 16-9. Device-Paced Burst Read Transfer351
Device-Paced Burst Write Transfer352
Figure 16-10. Device-Paced Burst Write Transfer353
External Bus Master Interface354
Arbitration354
Table 16-3. External Master Arbitration355
Table 16-4. Signal States During Hold Acknowledge (Holdack=1)355
Transaction Overview356
Single Read and Single Write Transfers356
Burst Read Transfer357
Figure 16-12. External Master Arbitration, Single Read and Single Write357
Burst Write Transfer358
Figure 16-13. External Master Burst Read358
External Master Error Interrupts359
Figure 16-14. External Master Burst Write359
EBC Registers360
Table 16-5. EBC DCR Addresses360
Table 16-6. External Bus Configuration and Status Registers360
Peripheral Bank Configuration Registers (Ebco_Bncr)362
Peripheral Bank Access Parameters (Ebco_Bnap)363
Error Reporting366
Error Locking366
Peripheral Bus Error Address Register (EBCO_BEAR)366
Peripheral Bus Error Status Register (EBCO_BESRO)367
Peripheral Bus Error Status Register 1 (EBCO_BESR1)369
PCI Overview372
PCI Bridge Features372
PCI Bridge Block Diagram373
Byte Ordering373
Figure 17-1. PCI Bridge Block Diagram373
Reference Information374
Table 17-1. Powerpc, Coreconnect PLB, and PCI Address Bit-Naming Conventions374
Table 17-2. Powerpc, Coreconnect PLB, and PCI Data Bus Bit-Naming Conventions374
PCI Bridge Functional Blocks375
PLB-To-PCI Half-Bridge375
Figure 17-2. PLB-To-PCI Half-Bridge Block Diagram375
PCI-To-PLB Half-Bridge376
PCI Arbiter376
Figure 17-3. PCI-To-PLB Half-Bridge Block Diagram376
Figure 17-4. Arbitration Structure376
PLB-To-PCI Address Mapping377
Table 17-3. PLB Address Map377
PCI-To-PLB Address Mapping379
Figure 17-5. PMM Register Sets Map PLB Address Space to PCI Address Space379
Table 17-4. PCI Memory Address Map379
PCI Target Map Configuration380
Figure 17-6. PTM Register Sets Map PCI Address Space to PLB Address Space380
PCI Bridge Transaction Handling381
PLB-To-PCI Transaction Handling381
PCI Master Commands381
PLB Slave Read Handling383
Prefetching383
PLB Slave Write Handling383
Aborted PLB Requests384
Retried PCI Reads384
PCI-To-PLB Transaction Handling384
PLB Master Commands385
Handling of Reads from PCI Masters386
Handling Writes from PCI Masters388
Miscellaneous388
Completion Ordering389
PCI Producer-Consumer Model389
Collision Resolution389
PCI Bridge Configuration Registers390
PCI Bridge Register Summary390
Table 17-7. Collision Resolution390
Table 17-9. PCI Configuration Address and Data Registers391
Table 17-10. PCI Configuration Register Offsets391
PCI Bridge Local Configuration Registers392
PMM 1 Mask/Attribute Register (PCILO_PMM1MA)395
PMM 1 PCI Low Address Register (PCILO_PMM1PCILA)395
Figure 17-10. PMM 0 High Address Register (PCILO_PMMOPCIHA)396
PCI Configuration Registers400
PCI Configuration Address Register (PCICO_CFGADDR)400
PCI Configuration Data Register (PCICO_CFGDATA)401
PCI Latency Timer Register (PCICO_LATTIM)407
PCI Header Type Register (PCICO_HDTYPE)407
Unused PCI Base Address Register Space408
Pcllnterrupt Control/Status Register (PCICO_ICS)413
Error Enable Register (PCICO_ERREN)413
Error Status Register (PCICO_ERRSTS)414
Bridge Options 1 Register (PCICO_BRDGOPT1)415
(Pcico_Plbbesro)418
PLB Slave Error Syndrome Register 1 (PCICO_PLBBESR1)418
PLB Slave Error Address Register (PCICO_PLBBEAR)419
Power Management Capabilities (PCICO_PMC)421
Power Management Control/Status Register (PCICO_PMCSR)421
PMCSR PCI-To-PCI Bridge Support Extensions (PCICO_PMCSRBSE)422
PCI Data Register (PCICO_DATA)423
Bridge Options 2 Register (PCICO_BRDGOPT2)423
Power Management State Change Request Register (PCICO_PMSCRR)425
Error Handling426
PLB Unsupported Transfer Type426
PCI Master Abort426
Bridge PCI Master Receives Target Abort While PCI Bus Master427
PCI Target Data Bus Parity Error Detection428
PCI Master Data Bus Parity Error Detection428
PCI Address Bus Parity Error While PCI Target429
PLB Master Bus Error Detection429
PCI Bridge Clocking Configuration430
PCI Power Management Interface430
Capabilities and Power Management Status and Control Registers430
Power State Control430
Changing Power States431
Address Map Initialization432
Other Configuration Register Initialization434
Table 17-12. Address Map Register Values434
Local Processor Boot from PCI Memory435
Configuration Cycles for Other Devices435
Timing Diagrams435
PCI Master Burst Read from SDRAM436
PCI Master Burst Write to SDRAM436
CPU Read from PCI Memory Slave, Nonprefetching436
CPU Read from PCI Memory Slave, Prefetching436
CPU Write to PCI Memory Slave436
PCI Memory to SDRAM DMA Transfer437
SDRAM to PCI Memory DMA Transfer437
Asynchronous437
Figure 17-60. PCI Master Burst Read from SDRAM439
Figure 17-61. PCI Master Burst Write to SDRAM443
Figure 17-62. CPU Read from PCI Memory Slave, Nonprefetching447
Figure 17-63. CPU Read from PCI Memory Slave, Prefetching450
Figure 17-64. CPU Write to PCI Memory Slave453
Figure 17-65. PCI Memory to SDRAM DMA Transfer457
Figure 17-66. SDRAM to PCI Memory DMA Transfer460
Synchronous463
Figure 17-67. PCI Master Burst Read from SDRAM463
Figure 17-68. PCI Master Burst Write to SDRAM471
Figure 17-69. CPU Read from PCI Memory Slave, Nonprefetching477
Figure 17-70. CPU Read from PCI Memory Slave, Prefetching479
Figure 17-71. CPU Write to PCI Memory Slave483
Figure 17-72. PCI Memory to SDRAM DMA Transfer487
Figure 17-73. SDRAM to PCI Memory DMA Transfer491
Chapter 18. Direct Memory Access Controller494
External Interface Signals494
Functional Overview495
Peripheral Mode Transfers495
Figure 18-1. DMA Controller External Bus Control Signals495
Memory-To-Memory Transfers496
Scatter/Gather Transfers497
Configuration and Status Registers497
Table 18-2. DMA Controller Configuration and Status Registers497
DMA Polarity Configuration Register (DMAO_POL)498
DMA Sleep Mode Register (DMAO_SLP)499
DMA Status Register (DMAO_SR)500
DMA Channel Control Registers (DMAO_CRO-DMAO_CR3)501
DMA Source Address Registers (DMAO_SAO-DMAO_SA3)503
DMA Destination Address Registers (DMAO_DAO-DMAO_DA3)504
DMA Count Registers (DMAO_CTO-DMAO_CT3)504
DMA Scatter/Gather Descriptor Address Registers (DMAO_SGO-DMAO_SG3)505
DMA Scatter/Gather Command Register (DMAO_SGC)506
Channel Priorities506
Data Parity During DMA Peripheral Transfers507
Errors507
Address Alignment Error507
Table 18-3. DMA Transfer Priorities507
PLB Timeout508
Slave Errors508
DMA Interrupts508
Table 18-4. Address Alignment Requirements508
Scatter/Gather Transfers509
Table 18-5. Scatter/Gather Descriptor Table509
Table 18-6. Bit Fields in the Scatter/Gather Descriptor Table509
Programming the DMA Controller510
Peripheral Mode Transfers510
Table 18-7. DMA Registers Loaded from Scatter/Gather Descriptor Table510
Figure 18-12. Memory to Peripheral DMA Transfer512
Memory-To-Memory Transfers513
Software-Initiated Memory-To-Memory Transfers (Non-Deviced Paced)514
Chapter 19. Ethernet Media Access Controller516
EMAC Features517
Figure 19-1. EMAC in a Typical Ethernet Application517
EMAC Operation518
Figure 19-2. Internal EMAC Structure518
MAL Slave Logic519
OPB Slave Logic519
Ethernet Address Match Logic519
Configuration and Status Registers519
Wake on LAN Logic519
Ethernet MAC520
EMAC Loop-Back Modes520
EMAC Transmit Operation520
Figure 19-3. EMAC Loop-Back Modes520
Arbitration between TX Channels521
Independent Mode521
Dependent Mode521
MAL TX Descriptor Control/Status Field522
Figure 19-4. MAL TX Descriptor Control/Status Field522
Early Packet Termination in Transmit524
Empty Packets524
Automatic Retransmission of Collided Packets524
Inter-Packet Gap (IPG) Tuning524
Full-Duplex Operation524
Figure 19-5. Transmit Packet Structure (Excluding VLAN Tagged and Control Packets)525
Table 19-1. FCS/SA Enable - Possible Configurations526
Table 19-2. Fcs/Pad Enable - Possible Configurations526
Table 19-3. FCSNLAN Tag Enable - Possible Configurations526
Figure 19-6. MAL RX Descriptor Control/Status Field527
Table 19-4. in Range Length Error Behavior for Various Packet Lengths528
Figure 19-7. Wake-Up Packet Format529
Figure 19-8. Control Packet Format531
Figure 19-9. Integrated Flow Control Mechanism532
Figure 19-10. Pause Operation State Machine533
Figure 19-11. Tagged MAC Packet Format534
Figure 19-12. Tag Control Information Field Structure534
Figure 19-13. Receive Address Recognition Flowchart537

IBM PowerPC 405GP

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