IBM PowerPC 405GP User Manual

The terms "single beat" or "1-S-byte," in reference to PLB transfers, refer to the M_size=OOOO
transaction type.
PCI bridge initiates the following commands as a PCI master:
• lID Read and lID Write
This command is generated
in response to PLB 1-S-byte read or write requests that decode to one
of the two
PCI lID spaces.
• Configuration Read and Configuration Write (type 0 and type 1)
This command is generated
in response to PLB 1-S-byte read or write requests that decode to the
PCICO_CFGDATA register.
• Memory Read
This command is generated in response to PLB 1-S-byte reads or byte and halfword burst reads
that decode to one of the three PMMs when the PMM is marked as nonprefetchable.
• Memory Read Line
This command is generated
in response to PLB 4- and S-word line reads or word and doubleword
reads of 32 bytes or less that decode to one of the three PMMs.
• Memory Read Multiple
This command is generated in response to PLB 1-S-byte reads or byte and halfword burst reads
that decode to one of the three PMMs when the PMM is marked as prefetchable. This command is
also generated in response to word and doubleword burst reads of greater than 32 bytes that
decode to one of the three PMMs. For prefetches, the
PCI bridge bursts up to a 64 bytes from the
PCI.
•
Memory Write
This command is generated
in response to PLB 1-S-byte writes or burst writes to one of the three
PMMs.
• Interrupt Acknowledge
This command is generated in response to a PLB 1-S-byte read from address OxEEDOOOOO.
• Special Cycle
This command is generated in response to a PLB 1-S-byte write to address OxEEDOOOOO.
The Memory Write and Invalidate command is not generated. All PCI memory writes are performed
with Memory Write.
The PLB
slave responds as a 64-bit device to word and doubleword bursts. All other commands
receive a 32-bit response.
The
PCI bridge supports PLB size 1-S-byte encodings. Burst reads of all sizes are also supported.
Read
line sizes greater than eight words are not supported, and no line writes are supported. The PCI
bridge posts all writes which are decoded to PCI memory and PCI lID space. Posted data is kept in
internal write buffers until it can be transferred to the PCI bus. All other writes and all reads are
connected, that is, they
complete on the PCI bus before completing on the PLB.
Preliminary
PCI Interface
17-11

IBM PowerPC 405GP Specifications

General

Brand	IBM
Model	PowerPC 405GP
Category	Computer Hardware
Language	English