Read Buffer
The
PCI bridge read buffer stores all read data (including delayed read and prefetched data) when the
data is received from the PLB, before it is passed to the
PCI. The 96-byte read buffer can store one
transaction.
Delayed Reads
A
delayed read is queued if a PCI master requests a read while PCI master writes are posted. Posted
writes are
completed on the PLB before the read is run. PCI bridge continues to post PCI master
writes (if buffer space is
available) while a delayed read is
in
progress. Such writes complete on the
PLB after the read, even though they
complete on the PCI before the read.
A
delayed read is also queued if data is not immediately available in the read buffer and a delayed
read does not already exist.
When a
PCI master returns for a previously requested delayed read, the data is passed out of the
read buffer.
While the PCI master accepts delayed read data, the PCI bridge can begin to prefetch
more read data, if the
PCI master posted write buffer is empty. See "Read Prefetching"
on
page 17-16
for more
details.
Any data remaining
in
the read buffer after delayed read data has been passed to a
PCI
master is
marked as prefetch data and discarded upon a write
in
either direction.
PCI bridge can hold one delayed read transaction. PCI bridge retries all other PCI master reads until
the
delayed read completes on the PCI. The read buffer discards data from a delayed read under only
one condition. The PCI discard timer is used to track the amount of time it takes for a PCI master to
re-request the read.
If
the PCI master does not re-request the read
in
2
15
PCI clocks (about one
millisecond for a 33 MHz PCI clock), PCI bridge discards the delayed read data. This timer begins
counting at the beginning of the
initial PCI cycle (delayed read request). If PCI bridge is used
in
a
system
on
which the PLB target (memory) maximum latency (including PLB arbitration) is a
significant portion of the timer duration, the timer can expire despite
normal bus operation. One
solution
to this problem is to disable the PCI Discard Timer.
If a delayed read is burst terminated on the PLB (a rare occurrence), PCI bridge will not repeat the
request
until the PCI master re-requests and only then if the PCI master requests more data than is
already buffered.
Read Prefetching
PCI bridge attempts to prefetch data to maximize burst throughput on PCI read requests. Read
prefetching occurs
only in response to Memory Read Multiple commands
or
Memory Read, if the PCI
target is programmed to treat them as Memory Read Multiple (Memory Read Line causes prefetching
to the next word boundary
only). This prefetch buffer is 96 bytes.
If a PCI master reads from the read buffer while a PLB read is in progress, data is passed to PCI as it
is being
filled from the PLB.
If
the read buffer goes empty long enough for the PCI subsequent latency
timer to expire, the PCI is target disconnected. If the read buffer fills
up,
the PLB cycle is master
terminated. The bridge PLB master
will not attempt to reacquire the PLB bus if its posted write buffer
is not empty.
Prefetched data is discarded if a write is accepted from either the PLB
or
the PCI. A PCI master read
that misses the prefetch buffer
also causes current read data to be discarded and the new request to
be serviced.
17-16
PPC405GP User's Manual Preliminary
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