OCMO_DSARC must be initialized before OCMO_DSCNTL[DSEN] is set to 1 to enable data-side
OCM accesses. See "OCM Initialization" on page 8-13 for details.
OSAR
~
1
0
51
6
Figure 5-4. OCM Data-Side Address Range Compare Register (OCMO_DSARC)
DSAR Data-side OCM address range
Reserved
5.4.4
OCM
Data-Side Control Register (OCMO_DSCNTL)
OCMO_DSCNTL enables and disables data-side OCM access.
OCMO_DSCNTL[DSEN] enables the OCM controller to respond to requests for data loads and stores
within the data-side
OCM address range defined by OCMO_DSARC[DSAR]. At reset,
OCMO_DSCNTL[DSEN] =
0;
data-side OCM is not enabled. If data-side OCM is to be accessed, this
field must be set to 1 during chip initialization, as described
in
"OCM Initialization" on page 8-13.
The reset value of the
DOF field is
1.
This field should always remain set to 1 when writing
OCMO_DSCNTL.
OS
EN
+
t
OOF
Figure 5-5. OCM Data-Side Control Register (OCMO_DSCNTL)
0
DSEN Data-Side OCM Enable
o Data-side OCM accesses are disabled.
1 Data-side
OCM accesses are enabled.
1
DOF This field should remain set to
1.
2:31
Reserved
Preliminary
On-Chip Memory
3
1
1
5-7
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