/*
Initialize vector table and interrupt handlers if not already done */
/*
--------------------------------------------------------*/
/*
Prepare system for asynchronous interrupts.
*/
/*
--------------------------------------------------------*/
/*
Initialize and configure timer facilities */
mtspr(PIT, 0);
mtspr(TSR, OxFFFFFFFF);
mtspr(TCR,
timecenable);
mtspr(TBL, 0);
mtspr(TBU, time_base_u);
mtspr(TBL,
time_base_I);
mtspr(PIT,
pit_count);
/*
Initialize the MSR
/*
clear PIT so no PIT indication after TSR cleared*/
/*
clear TSR */
/*
enable desired timers */
/*
reset time base low first to avoid ripple */
/*
set time base,
hi
first to catch possible ripple */
/*
set time base, low */
/*
set desired PIT count */
*/
/*
Exceptions must be enabled immediately after timer facilities to avoid missing a */
/*
timer exception. */
/*
~
1*
The MSR also controls privileged/user mode, translation, and the wait state. */
/*
These must
be
initialized by the operating system or application code. */
/*
If enabling translation, code must initialize the TLB. */
~
~
mtmsr(machine_state);
~ ~
/*
Initialization of other processor facilities should be performed at this time. */
~ ~
~
~
1*
Initialization of non-processor facilities should be performed at this time. */
~ ~
~ ~
/*
Branch to operating system or application code can occur at this time. * /
~
~
Preliminary Reset and Initialization 8-17
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